I see in the documentation site that ARM offers up some bus functional models to simulate both a 32 and a 64 bit AHB bus master in Verilog RTL.
Where do I find these models, and what is the cost?
I am working to verify a customer's AHB peripheral, and don't really want to write my own bus functional model..
There seem to be a number of options hinted at in the documentation area. One such example:
cmsdk_ahb_fileread_master32.v
Does this answer your question gordwait?
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