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How the PE accesses peripherals registers and memories?


I was reading this document and found that figure A.11 describes that platform can have on-chip devices connected to the SMMU and peripherals connected through a non-coherent interconnect.

I thought that PE can access all peripherals on the platform through the SMMU, but what is the difference between those two different device types? 

If anyone can provide examples of the peripheral and on-chip devices, it would be really helpful to understand those two different types of devices.



How the memory-mapped devices/registers can be accessible by the PE on ARM architecture?

When It comes to the SMMU, the physical registers of the SMMU for example page 0 registers (e.g., SMMU_IDR0) can be read/written just as exactly same as accessing any other memories with ldr/str instruction. 

Or another example would be frame buffer. It seems that PE can access frame buffer addresses which is pre-configured on the board as exactly same as accessing SMMU registers with generic ldr/str instructions.

In the above figure what would be the path from PE to the memories or registers of the memory transactions? Does it go through the SMMU? or directly goes to the peripherals without going through the SMMU??


Also, it seems that pre-configured physical addresses are used for accessing the peripheral's registers and memories. Does it also mean that the memory transactions of the PE for accessing peripherals registers and memories will be governed by the GPT?