stage2 translation fault ,post-indexing instructions invalid when virtualizing , the ISV bit is 0.

We use a hypervisor(ARM64), if a guest accessed memory outside of a memslot (handle mmio)using any of the load/store instructions in the architecture which doesn't supply decoding information in the ESR_EL2 (the ISV bit is 0),

data abort with invalid syndrome.

For instance, a baremetal OS can use any of the following post-indexing instructions, where
x1 contains the address of the MMIO region:

1.      ldr     x2,    [x1],    #8
2.      ldr     w2,    [x1],    #-4
3.      ldr     x2,    [x1],    #-8
4.      ldr     w2,    [x1],    #4
5.      ldrh    w2,    [x1],    #2
6.      ldrb    w2,    [x1],    #1
7.      str     x2,    [x1],    #8
8.      str     w2,    [x1],    #-4
9.      strh    w2,    [x1],    #2
10.     strb    w2,    [x1],    #1

but in hypervisor the ISS.ISV is 0, hypervisor can't handle the MMIO access when stage2 translation fault.

ARM DDI 0487G.a  D13-3147

ISV, bit [24]

Instruction Syndrome Valid. Indicates whether the syndrome information in ISS[23:14] is valid.

0b0 No valid instruction syndrome. ISS[23:14] are RES0.

0b1 ISS[23:14] hold a valid instruction syndrome.

In ESR_EL2, ISV is 1 when FEAT_LS64 is implemented and a memory access generated by an

ST64BV, ST64BV0, ST64B, or LD64B instruction generates a Data Abort for a Translation fault,

Access flag fault, or Permission fault.

I want to know why this is happening？ Why are these post-indexing instructions invalid when virtualizing？ Is there any design consideration?