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Hello,
Is there any data regarding the minimum and maximum frequency a processor can operate in ARM V-7 ?
Thank you daith.
That's mostly an implementation choice - the first Cortex-A8 implementations used some semi-custom layout and cells to improve performance - but the synthesis tools and standard libraries soon caught up, so there is also a fully synthesized version which is commonly used today.
HTH, Pete
And daith is right that there is no minimum execution speed. All the cores are designed to be safely clock gated, which means they can effectively operate at frequencies all the way down to zero.
This seems to conflict with the article I quoted below, if dynamic logic is indeed used then there would be a minimum right? Of course still very much dependent on the implementation / process (and temperature!). I do know they can safely run at very low speeds1, but I would not feel comfortable completely gating their clock indefinitely at an arbitrary moment. (Of course one would normally never stop the clock with a pipeline full of instructions, but rather at a WFI or such.)
11the TI SoC I use has an option to switch the cortex-A8 to run on the 32768 Hz RTC clock as a low power mode. Makes the serial console funny to use: all that's missing is the sound of an old TeleType.
From an article on the Cortex-A8 design (emphasis mine):
Finally, a few of the most critical timing and area sensitive blocks of the design are reserved for full custom techniques. This includes memory arrays, register files and scoreboards. These blocks contain a mix of static and dynamic logic. No self-timed circuits are used.
That's right. The maximum frequency achievable by any particular core would depend not just on the implementation of the core itself but also on the silicon process and design rules used to fabricate it. And daith is right that there is no minimum execution speed. All the cores are designed to be safely clock gated, which means they can effectively operate at frequencies all the way down to zero.
Hope this helps
Chris
Wouldn't that be up to the individual SoC designers and manufacturers? I believe the ARM IP uses static logic so there's no built in minimum frequency which makes it easier to adapt, but other designs may use dynamic logic as in DRAMS as it can sometimes save on logic or give extra speed.