Dear all,
As I know there are separate vectors to handle SError caused by EL0 and EL1.
My queston is follow:
Due to fact that SError is asynchronous, can I rely on fact that if cpu entered serror_el1_vector to handle SError, then SError was caused exactly in EL1 (not in EL0, EL2, EL3) and if cpu entered serror_el0_vector then SError was exactly caused in EL0? Another word, is it possible folowing case:
1. EL0:
1.1. incorrect access to some device register (for ex. write to RO register) that cause SError interrupt. Such access does not generate access error immediately, but at some point later when AXI transaction actually happened the memory system returns a fault, which is reported as asynchronous abort.
1.2. SError still not generated and user make svc to enter EL1
2. EL1:
2.1. Now cpu in EL1 mode enetered by step 1.2
2.2. SError caused by step 1.1 finally generated but now cpu in EL1, not in EL0, so in which vector cpu will enter to handle SError: serror_el1_vector or serror_el0_vector ?
Thank you in advance!