Hello and I welcome you to my Arm programming tutorial series. I would like to give a big thank you to Abhishek Agrawal, a Final Year Undergraduate Student at IIT Kharagpur for his help to complete this blog.
Let’s start with basics. RISC machines have become very powerful these days. Arm processors are completely based on the RISC architecture. This approach reduces the costs of hardware and it produces less heat than traditional x86 architectures hence it is power efficient. It has highly optimized instruction sets.
RISC architecture is also known as Load-Store Architecture, it means CPU cannot directly perform memory operation. For memory operation microcontroller have to first load desired memory location content in a registers then after CPU operation it can store the result through general purpose registers.
Arm microcontrollers are the most widely used microcontroller in the world. About 98% of all mobile phones sold use at least one Arm processor.
Instructions for Arm cores have 32-bit wide fixed-length instructions, but later versions of the architecture also support a variable-length instruction set that provides both 32 and 16-bit wide instructions for improved code density. Currently Arm microcontrollers have 32-bit architectures in most mobile phones and embedded hardware.
More recently, the Armv8-A architecture adds support for a 64-bit address space and 64-bit arithmetic. It is more power efficient and has greater performance range.
Arm has three series of microcontrollers: Arm Cortex-A, Arm Cortex-R and Arm Cortex-M.
Cortex-A microcontrollers are intended for application specific systems such as smartphones.
Cortex-R is a real-time specific microcontroller, used in applications such as space and missiles.
Cortex-M is used in general purposes applications such as motor control, LED, LCD interfaces and more.
The rm Cortex-M series has five sub-series of microcontrollers:
The interesting thing is that all microcontrollers are consistently based on 32-bit processor architecture. However, few of them are using a 16-bit thumb instruction set, and the rest of them are using both thumb and the Arm instruction set.
Arm Cortex-M0 is mostly preferred where the requirement is low power and low cost. It includes almost all the features of a microcontroller. It has Nested Vectored Interrupt controller which is also known as NVIC. The NVIC is tightly coupled to the processor core. This facilitates low latency exception processing. The main features include:
Another important feature is wake up interrupt controller (WIC) interface.
Wake up Interrupt Controller (WIC) can detect an interrupt and wake the processor even from deep sleep mode where the processor is resting in minimum power consumption mode. Wireless sensor networking uses this feature for the lowest possible power consumption.
Another Important feature is Data WatchPoint and BreakPoint. It is a feature of the debug unit which is present on-chip. In debug mode we can monitor the state of the processor in each and every clock.
Arm Cortex-M0+ is a superset of the Cortex-M0 processor in term of instruction set. i.e. the Cortex-M0 instruction set is 100% compatible with Cortex-M0+ processors. Cortex-M0+ low latency I/O Interface provides “Harvard- like” access to peripherals. It improves overall cycle efficiency for I/O access.
Arm Cortex-M3 adds more features to the Cortex-M0+ sub-series processors. The main feature of this processor is 1-cycle 32-bit hardware multiply, 2-12 cycle 32-bit hardware divide, and saturated math support.
Cortex-M4 is a Cortex-M3 plus DSP Instructions, and also optional floating-point unit (FPU) on chip. If a core contains an FPU then it is known as a Cortex-M4F core microcontroller - otherwise it is only a Cortex-M4 microcontroller.
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