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RTL function disables jtag

I am trying to use RTL for the tcp communication part on the lpc2368 project. The stack ran ok on the lpc2378, but on 2368 it appears that the function Init_Tcpnet() somehow disables a jtag. After this function is executed, jtag doesn't connect anymore, giving an error "can't stop arm device". The only way to restore connection is to erase a chip with Flashmagic.
If I insert a loop before Init_Tcpnet(), connection never fails.
Pins and functions for ethernet are exactly the same for 2378 and 2368, so the reason is not in pin configuration, but somwhere else.
Did anybody have a similar problem?

Gennady

Parents
  • I've put a delay of 2S at the beginning of main().
    Now behaviour is a little bit different.
    Debug session always starts, and if Init_Tcpnet() is not there, everything is ok.
    If Init_Tcpnet() is present, any attempt to stop a processor leads to the following:
    - message "Could not stop ARM device!" appears.
    - on 'OK' 'Stop' icon greys out and 'Run' icon appears.
    - attempt to run leads to dropping out of the debug session.

    There are 2 things I can think about:
    1. hardware - PHY initialization. I beleive that Init_Tcpnet() includes PHY initialization, so possible hardware problems probably can lead to the above behavior.
    2. I am using ULINK jtag, not ULINK2. Fmax is 200KHz (I also tried 100KHz). Are there any issues with ULINK that can lead to the problem?

Reply
  • I've put a delay of 2S at the beginning of main().
    Now behaviour is a little bit different.
    Debug session always starts, and if Init_Tcpnet() is not there, everything is ok.
    If Init_Tcpnet() is present, any attempt to stop a processor leads to the following:
    - message "Could not stop ARM device!" appears.
    - on 'OK' 'Stop' icon greys out and 'Run' icon appears.
    - attempt to run leads to dropping out of the debug session.

    There are 2 things I can think about:
    1. hardware - PHY initialization. I beleive that Init_Tcpnet() includes PHY initialization, so possible hardware problems probably can lead to the above behavior.
    2. I am using ULINK jtag, not ULINK2. Fmax is 200KHz (I also tried 100KHz). Are there any issues with ULINK that can lead to the problem?

Children
  • Yes, it was a hardware problem. PHY oscillator was connected incorrectly and gave non-standard clock (and consequently no clock to the processor from PHY).
    Absence of this clock somehow affected jtag connection.
    Anyway, I am glad it's resolved now.

    Thank you for the response.