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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3661 Questions
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  • Suggested Answer

    Which bit of WSTB should be set to 1? 0

    847 views
    1 reply
    Latest 10 months ago
    by Ben Hicks Arm Employee Badge
  • Suggested Answer

    AXI4 Channel Handshake 0

    • AXI4
    948 views
    1 reply
    Latest 10 months ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    Additional info on a particular MPU configuration 0

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    1 reply
    Latest 11 months ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    FPU op performance degradation in a very specific case 0

    • High Performance Computing (HPC)
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    0 replies
    Started 11 months ago
    by Dmitrii Klementev
  • Not Answered

    a TCM ECC error can cause WFI to fail in the ARM R52+ architecture (Armv8‑R, Arch32) 0

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    "Test Target" instructions - only consider SAU / IDAU, or also PPC & MPC 0

    1373 views
    1 reply
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  • Answered

    the AMBA AHB bus master interface to start a burst with only 1 data transfer without the HSEL signal 0

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    1696 views
    1 reply
    Latest over 1 year ago
    by Colin Campbell Arm Employee Badge
  • Suggested Answer

    APB 0

    • APB
    856 views
    1 reply
    Latest over 1 year ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Is it normal that DC CVAC does also carry out a cache line invalidate on Cortex-A53? 0

    • Cache coherency
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  • Answered

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    Latest over 1 year ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

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    • Security
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    1 reply
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    by Martin Weidmann Arm Employee Badge
  • Answered

    Unable to write to memory region marked as both writable and executable on cortex-R82 0

    • Cortex-R82
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    2061 views
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    Latest over 1 year ago
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  • Not Answered

    M0 GPIO level-sensitive interrupt, how many minimal CPU cycles? 0

    • Cortex-M0
    • Interrupt Handling
    523 views
    0 replies
    Started over 1 year ago
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    • performance
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    2297 views
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    Latest over 1 year ago
    by Christopher Tory Arm Employee Badge
  • Answered

    Correctly invalidating Cortex-A53 shared L2 cache for access through ACP? +1

    • Cortex-A53
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    Latest over 1 year ago
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  • Suggested Answer

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  • Answered

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    • AArch64
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  • Not Answered

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    • Helium
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