• State Accepted Answer
  • +1 person also asked this people also asked this
  • Locked Locked
  • Replies 4 replies
  • Subscribers 347 subscribers
  • Views 8080 views
  • Users 0 members are here
Options
Related
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

[Cortex-A53] STP instruction stores out of the specified memory

Emmy0

Hi Experts，

     I have a question about "STP" instruction in Cortex-A53.

     STP W6, W6, [SP, #20]  --> after it executes, the memory of [sp, #16] and [sp, #28] are corrupted.

     I don't know why cause it. 

    Can you help to explain the reason? 

    The environment is:

       Before STP executes:

             W6=0x10, SP=0xFFFD36D0, MMU disable, dcache disable, icache enable.

             memory content is:

             [0xFFFD36E0]:  0xFFFD3740 0x00000000 0x00000001 0xFFFD3750

      After STP executes:

             memory content is:

             [0xFFFD36E0]:  0x00000000 0x00000010 0x00000010 0x00100000

      Thanks for your attention!

Best Regards,

Emmy

Parents
  • 0 in reply to MarekBykowski

    Hi MarekBykowski,

         Thanks for your explaintion!

         If I map the region to memory, the issue is disappeared.

         But if the region is changed to DDR which is connected AXI bus, under the same environment(no MMU, device type), the code can work well.

         Does it be related to the different bus interfaces? AXI is ok, but AHB is wrong.

Reply
  • 0 in reply to MarekBykowski

    Hi MarekBykowski,

         Thanks for your explaintion!

         If I map the region to memory, the issue is disappeared.

         But if the region is changed to DDR which is connected AXI bus, under the same environment(no MMU, device type), the code can work well.

         Does it be related to the different bus interfaces? AXI is ok, but AHB is wrong.

Children
  • 0 in reply to Emmy0

    Emmy0: AXI is ok, AHB is wrong

    I don't think AHB is wrong. For example the Static Memory my board is using is connected to the CCN (Cache Coherent Network) through AXI4, not AHB. AHB is less offering and less complex and eg. Coresight uses it. 

    For the AXI4 behind Static Memory I can run equally well the code being attributed to the Devices and Memory.

  • 0 in reply to MarekBykowski

    Hi MarekBykowski,

         Yes, if Static Memory via AXI4, it works well.

         Unfortunately, my board's Staic Memory is connected AHB, so STP access address is restricted  to 64-bit align. I have worked around in code to avoid "STP" generation. Now it can work.

          Thanks!

    Best Regards,

    Emmy