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How AXI Handle unaligned transfer in FIX and INCR mode.

How AXI Handle unaligned transfer in FIX and INCR mode.

Please consider following example:

CASE 1)

Data bus width = 32 bit

awsize = 1

awlen = 3

Address = 0x03

burst type = FIXED.

CASE 2)

Data bus width = 32 bit

awsize = 1

awlen = 3

Address = 0x03

burst type = INCR.

are these invalid transfer or AXI will handle this?

#RTLDesign,#verilog,#digitaldesign,#arm,#AXI4

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