Hi all I have interfaced 64K SRAM and 8255 PPI to 8051RD2 for scanning Matrix keyboard. On resetting the system all port pins of 8255 go to high impedence state. i am using Memory map technique to access 8255 resources.Latch and decoders are used to enable them. Port A:0x8000 Port B:0x8001 Port C:0x8002 Port CW:0x8003 required PCL = o/p PCH = i/p,PortA=PortB=i/p on Power reset 8255 is given 0x9B from 8051 while 8255 is accessed SRAM is disabled. After codes are executed nothing seems to happen.8255 is enabled while it is reffered by using above address. How can i go forward to make this ckt working ? ie atleast first to set-reset port pins. for proper 8255 reset i have tried two ckts a)reset signal of 8051 was given to NPN transistor to invert it. b)resistor capacitor combination,where res(10K)-->VCC,capacitor(10uf)-->gnd ckt response was same with both. where things might be going wrong ? while i was manually connecting PC.0 pin to gnd,All other pins of PC turned to same voltage,even when they are not shorted to each other. Should i give pull up to port Pins ? Regards Naresh
Hi, You mention that you are using a 64K SRAM that covers 0x0000 - 0xFFFF and it seems to me that you are then mapping the 8255 into 0x8000 - 0x8003 which is right into the middle of its address range, are you sure this is what you want? You need to program the control register with 0x9A to give you PCL= o/p (0x9B makes PCL= i/p). The reset for the 8255 is the same polarity as the 8051 so however you reset it, it should hopefully (I use a watchdog chip which can easily reset several devices) be ok use it to reset both devices.
Hi Mark Thanks for reply. At present i am using only 8K out of 64k SRAM,so decoding logic enables 8255 for 0x8000..0x8003 and SRAM for address range less than 0x8000. Can following be the cause of problem: Suppose if A3,A4,A5 lines are used in decoding logic,since this lines are multiplexed which carry ADDR during ALE = 1 and then DATA. So should this lines be taken after Latch ckt where Address is stable even if lines are changed for DATA mode. i will get back after checking above condtn and working of reset ckt Regards Naresh Rana
Hi, Yes if you are using any of A0 to A7 as part of the address decoding they do need to be taken after they have been latched - I think we use a 74HC373 to latch the address lines. Initially (if you arent already) I think you can use A15 and feed it into an inverter to provide the chip select signal for the 8255 and for now accept that the chip is mapped into the upper 32k address range. I also think that you will need pull-up resistors as I assume you are looking for a low on the i/p port - i cant be more specific at the moment as it is a long time since i did s/w for a scanned keypad, but i will try and provide you with more info if you need it. Mark.
Hi Mark Thanks.MController is able to read 8255 portC, i think Reset Ckt was creating problem,which i seperated from main. i have provided pull up to PORTC. i would be happy if u can share more info on this,also is it possible to generate interrupt of keyboard using 8255 ? regards Naresh Rana
Hi Naresh, I am not sure what further info you need, I dont think you can program the 8255 to generate an interrupt (i might be wrong) but even if you can, as you are doing a scanned 4x4 matrix, I think you need to use one of the 8051 timers and program it to (for example) generate an interrupt every 1ms. so that you can select the next keyboard o/p line and read each return line on PCL during this interrupt. This way you will of read all the keys every 4ms. Mark.