Any suggestions for a cycle accurate simulator for Cortex-M devices other than Keil. We are currently using Keil uVision and came across some issues regarding the timing of a routine and would like to try another option.
What we are looking for is an instruction set simulator that can accurately report timing of the actual hardware.
for Cycle Accurate models of Cortex-M cores, take a look at the The specified item was not found. website: IP Vendor Selection. They currently have support for the Cortex-M0, Cortex-M0+, Cortex-M3 and Cortex-M4.
Hi billneifert, would you like to weigh in?
Hi Rob and Alban, thanks a lot for following up on my post. I took a look at the CDS website and it seems that they provide hardware (RTL) models for SoC designs. We are looking for a software simulator similar to Keil or OVPsim (which is not cycle-accurate). Any other options?
Hi Hanni, the models offered by Carbon Design Systems are indeed generated from RTL but they are software models (don't require a hardware simulator) and have been integrated with RVDS/DS-5 debuggers from ARM as appropriate. We of course also have a large amount of additional instrumentation data available as well to give the designer a complete understanding of the actual cycle by cycle impact of software on the underlying hardware system. We also offer a number of pre-built reference systems (which we call Carbon Performance Analysis Kits or CPAKs) for the M0, M3 and M4 cores on our Carbon System Exchange portal. These are great starting points for software development and, depending upon your actual system configuration, can often get you up and running with your own software within minutes of download.
Since our models and systems are compiled from the actual RTL implementation, you can have 100% confidence that the cycle numbers reported will be the same as actual silicon. I would of course be happy to answer any additional questions you have.
I see Bill from Carbon has replied with more detail. The ISSs from ARM for the Cortex-M family (in MDK and Fast Models) provide full functional accuracy but are loosely timed (LT) models. They would not give you the accurate timing that you are looking for.
Thanks for the product overview. The CPAK option sounds really interesting especially that we don't want to upgrade to DS-5 right now.
I do have a couple of questions on CPAK:
1. Would we be able to debug our application at the instruction level granularity with CPAK? What I mean is that we need to get a cycle-by-cycle view of what is going on in the processor.
2, Which ARM compiler is CPAK compatible with? We use GNU gcc (gcc-arm-none-eabi-4_9-2015q1-20150306).
Thanks Rob, that explains why we are having trouble correctly timing some of the routines in our application.
Hi Hanni, I think the CPAK sounds very well-suited for what you're looking to do. CPAKs execute in SoCDesigner which means that you can take advantage of all of SoCDesigner's debug and analysis capabilities. This means that we offer source level debugging via our interface to RVDS/DS-5 or you can alternatively use the built-in disassembler which comes with the tool. The analysis capabilities of SoCDesigner let you view what is going on in both the software and hardware on a per-cycle basis. You can even synchronize the analysis window to see the exact number of cycles from when a software line executes and any event in hardware.
The ARM processor models which run in our CPAKs run un-modified ARM binaries so compiler versions aren't a problem. If you're running your application today on any other ISS model then it should have no problems running on our CPAKs.
We would be happy to set up a demonstration of any of our CPAKs and walk you through all that we can do. Please feel free to contact me directly and I can set that up. My email is email@example.com. We can of course just continue to exchange information here as well however if you would prefer that.
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