freeRTOS demo DS-5 ERROR(CMD360) when trying to debug

Hello,

I'm trying to program a Cyclone V SoC using DS-5 and I get the following errors:

Stopping running target Intel SoC FPGA - Cyclone V SoC (Dual Core) on connection
Connected to running target Intel SoC FPGA - Cyclone V SoC (Dual Core)
Execution stopped in SVC mode at S:0x3FF8D94C
S:0x3FF8D94C   B        {pc}-0xc ; 0x3ff8d940
cd "D:\UserData\z0045mwh\Documents\DS-5 Workspace"
Working directory "D:\UserData\z0045mwh\Documents\DS-5 Workspace"
Execution stopped in SVC mode at S:0x3FF8D94C
S:0x3FF8D94C   B        {pc}-0xc ; 0x3ff8d940
source /v "C:\intelFPGA\18.1\embedded\ds-5\sw\debugger\configdb\Scripts\altera_target_check.py"

No SYSID registers could be found. Has a peripheral description file been supplied?

source /v "D:\UserData\z0045mwh\Documents\DS-5 Workspace\FreeRTOSv10.3.1\FreeRTOS\Demo\CORTEX_A9_Cyclone_V_SoC_DK\preloader.ds"
+stop
WARNING(CMD315): Target is not running
+wait 5s
+reset system
+wait 5s
+loadfile "$sdir/uboot-socfpga/spl/u-boot-spl" 0x0
Loaded section .text: S:0xFFFF0000 ~ S:0xFFFF671B (size 0x671C)
Loaded section .rodata: S:0xFFFF671C ~ S:0xFFFF82E4 (size 0x1BC9)
Loaded section .data: S:0xFFFF82E8 ~ S:0xFFFF91AF (size 0xEC8)
Entry point S:0xFFFF0000
Target has been reset
Execution stopped in SVC mode at S:0x3FF8D94C
S:0x3FF8D94C   B        shift+1073273152 ; 0x3FF8D940
+set debug-from *$entrypoint     # Set start-at setting to address of $entrypoint
+start
Reloading program
Starting target with image D:\UserData\z0045mwh\Documents\DS-5 Workspace\FreeRTOSv10.3.1\FreeRTOS\Demo\CORTEX_A9_Cyclone_V_SoC_DK\uboot-socfpga\spl\u-boot-spl
Running from entry point
Execution stopped in SVC mode at S:0xFFFF0000
In start.S
Unable to read source file D:/SJ/nightly/14.0/200/w64/acds/embedded/examples/hardware/av_soc_devkit_ghrd/software/preloader/uboot-socfpga/arch/arm/cpu/armv7/start.S
S:0xFFFF0000   39,0   B        reset ; 0xFFFF0070
+delete
All user breakpoints deleted
+tbreak spl_boot_device
Breakpoint 2 at S:0xFFFF110C
    on file spl.c, line 70
    on file spl.c, line 80
+cont
+wait 60s
ERROR(CMD360):
# in D:\UserData\z0045mwh\Documents\DS-5 Workspace\FreeRTOSv10.3.1\FreeRTOS\Demo\CORTEX_A9_Cyclone_V_SoC_DK\preloader.ds:46 while executing: wait 60s
! Wait for stopped timed out
ERROR(CMD656): The script D:\UserData\z0045mwh\Documents\DS-5 Workspace\FreeRTOSv10.3.1\FreeRTOS\Demo\CORTEX_A9_Cyclone_V_SoC_DK\preloader.ds failed to complete due to an error during execution of the script
loadfile "D:\UserData\z0045mwh\Documents\DS-5 Workspace\FreeRTOSv10.3.1\FreeRTOS\Demo\CORTEX_A9_Cyclone_V_SoC_DK\Debug\RTOSDemo.elf"
ERROR(CMD16-TAD11-NAL33):
! Failed to load "RTOSDemo.elf"
! Failed to write 8 bytes to address N:0x0010C2D8
! Target is running, cannot access.
set debug-from main
start
ERROR(CMD350): Command not possible when running
wait

I'm also looking at the UART0 output and see this output:

data abort

    MAYBE you should read doc/README.arm-unaligned-accesses

pc : [<ffff018c>]          lr : [<ffff0074>]
sp : 3ff35630  ip : 00000010     fp : 00000001
r10: 3ffa2bb1  r9 : 3ffaceb8     r8 : 3ff35f60
r7 : 00000001  r6 : 3ffae32c     r5 : 400001a7  r4 : ffff8368
r3 : 00000000  r2 : c0000000     r1 : 00000048  r0 : 40000173
Flags: nZcv  IRQs off  FIQs off  Mode SVC_32
Resetting CPU ...

resetting ...

U-Boot SPL 2013.01.01 (Apr 08 2018 - 17:00:50)
BOARD : Altera SOCFPGA Cyclone V Board
CLOCK: EOSC1 clock 25000 KHz
CLOCK: EOSC2 clock 25000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 800 MHz
CLOCK: DDR clock 400 MHz
CLOCK: UART clock 100000 KHz
CLOCK: MMC clock 50000 KHz
CLOCK: QSPI clock 3125 KHz
RESET: WARM
INFO : Watchdog enabled
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
SDRAM: 1024 MiB
ALTERA DWMMC: 0
reading u-boot.img
reading u-boot.img


U-Boot 2013.01.01 (Apr 08 2018 - 17:02:43)

CPU   : Altera SOCFPGA Platform
BOARD : Altera SOCFPGA Cyclone V Board
I2C:   ready
DRAM:  1 GiB
MMC:   ALTERA DWMMC: 0
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Skipped ethaddr assignment due to invalid EMAC address in EEPROM
Net:   mii0
Warning: failed to set MAC address

Hit any key to stop autoboot:  0
reading u-boot.scr
** Unable to read file u-boot.scr **
Optional boot script not found. Continuing to boot normally
reading zImage
** Unable to read file zImage **
reading socfpga.dtb
** Unable to read file socfpga.dtb **
Bad Linux ARM zImage magic!
SOCFPGA_CYCLONE5 #

Am I running into some problem because there is already a Linux kernel on the HPS already? Any help is greatly appreciated.

Parents Reply Children
More questions in this forum