How to make Ethos-U NPU work on an ARM Cortex-A + Cortex-M processor?

I have a question about how to make Ethos-U NPU work on a ARM Cortex-A + Cortex-M processor. First, I found ethos-u-linux-driver-stack and ethos-u-core-software on https://git.mlplatform.org/.

1. I know ethos-u-linux-driver-stack is Ethos-U kernel driver. Should it be integrated into the Linux OS running on Cortex-A or be integrated into the Linux OS running on Cortex-M? I am nor clear about which core it need to perform on.

2. For ethos-u-core-software, how to run it? I did't find the detail steps to run it. Does it run on NPU or any core?

3. Except the above two repos, is there any other repo necessory to make Ethos-U NPU work on an ARM Cortex-A + Cortex-M processor?

Thanks for your suggestion in advance.

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  • Hi, Kristofer,

    Recently I have some hardware questions about ethos-u65. Could you give me some guide?

    For field shram_size in CONFIG register, I see there are two values, SHRAM_48kB and SHRAM_96kB.

    1. Is the size fixed or changeable by resetting some register?
    2. Does SHRAM mean shared RAM? Is it SRAM?
    3. Is it the RAM in NPU itself or the RAM on processor/microcontroller?

    For DMA controller, I see there are several channels.

    1. For command channel, it mentions NPU uses this channel to read the command stream, normally from external flash. Is it ok for the command steam located in DRAM?
    2. For IFM channel and weight channel, the data is transferred from external memory to the shared RAM. Is the shared RAM big enough to save the ifm and weight for a vela model generated by vela tool + ssd mobilenet tflite model?

    For Arm AMBA 5 AXI interfaces, there are two read/write master M0 and M1.

    1. Is M0 used by the NPU to access higher data rates memory, such as on-chip SRAM? And is M1 used by the NPU to access memory, such as DRAM?
    2. When do M0 work and when does M1 work? Should we configure them in software? I am quite unclear about it.
Reply
  • Hi, Kristofer,

    Recently I have some hardware questions about ethos-u65. Could you give me some guide?

    For field shram_size in CONFIG register, I see there are two values, SHRAM_48kB and SHRAM_96kB.

    1. Is the size fixed or changeable by resetting some register?
    2. Does SHRAM mean shared RAM? Is it SRAM?
    3. Is it the RAM in NPU itself or the RAM on processor/microcontroller?

    For DMA controller, I see there are several channels.

    1. For command channel, it mentions NPU uses this channel to read the command stream, normally from external flash. Is it ok for the command steam located in DRAM?
    2. For IFM channel and weight channel, the data is transferred from external memory to the shared RAM. Is the shared RAM big enough to save the ifm and weight for a vela model generated by vela tool + ssd mobilenet tflite model?

    For Arm AMBA 5 AXI interfaces, there are two read/write master M0 and M1.

    1. Is M0 used by the NPU to access higher data rates memory, such as on-chip SRAM? And is M1 used by the NPU to access memory, such as DRAM?
    2. When do M0 work and when does M1 work? Should we configure them in software? I am quite unclear about it.
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