I have an 8 processor FVP. I can run independent code by branching on the value of MPIDR. When I do stores to the same 64 byte word, from different processors, the results are not coherent.
cpuN does a STRB to (address + N) of value 0x11. I then do a LDR of address (8 bytes) to see the result. On each processor, I see the STRB wrote the single byte in the word. If the L2 caches were coherent, whoever wrote after the first write would fetch the current Modified value from the first write, and I would see both bytes in the result. I do not.
All the parameters I can think of in the list, and mentioned in the documentation, say I should be coherent. Any idea why it is not working?
Found it, third time through the manual. bp.secure_memory=0 is required for the DRAM to work in Base_RevC. Before that, I could write to my local cache, but there was no point of hierarchy which merged writes.
Note that this also requires (if doing PA=VA) that you only map to addresses within 0x8000_0000 to 0xffff_ffff if dram_size=2 (the default value).
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