The Arm ML Research Lab explores cutting edge techniques and state-of-the-art algorithms. One of our primary research thrusts is investigating ways to bring more machine learning applications to Arm's products, and make existing applications more efficient. Machine learning algorithms, and neural networks (NNs) in particular, are increasingly deployed in very constrained devices. Popular applications include visual and speech interfaces in smart-home devices, predictive maintenance for commercial and industrial machines, and health monitoring in wearable devices. However, due to the energy, power, storage, and compute limitations of these devices, they are frequently limited to simplistic tasks, while more sophisticated requests are off-loaded to a more capable device or to a server. Frequently, even off-loading is not practical due to the additional latency and energy costs, crippling the intelligence available in constrained devices.
However, two of our projects at Arm have significantly advanced the state of the art in dramatically reducing the complexity and size of neural networks, bringing us closer to successfully running more complex tasks on such applications.
The size of typical RNN layers can prohibit deployment of these networks on IoT devices, or reduce the efficiency of the execution of these networks on devices with small capacity caches. An LSTM-based keyword spotting network, for example, has a model size of 243KB, which exceeds the amount of SRAM available in many microcontroller-based systems and even exceeds the total storage capacity of some. Thus, there is a need for a compression technique that can drastically compress RNN layers without sacrificing the task accuracy.
The research in neural network (NN) compression can be roughly categorized under four topics: Pruning, Structured Matrix-based Techniques, Tensor Decomposition, and Quantization (see 'References' for examples). However, our results show that these popular compression techniques can lead to significant losses in accuracy when attempting to compress networks by a factor of 15 or more. Additionally, a compression technique should not sacrifice run-time during inference, as some of these applications can have hard real-time deadlines. In this work, we provide an alternative to the traditional approaches that can achieve these objectives; Kronecker Product RNNs.
Given matrices B and C, the Kronecker Product A can be expressed as:
Where ◦ is the Hadamard product. B and C can be referred to as the Kronecker factors of A. We use the Kronecker factors to replace the recurrent weights of RNNs. Prior work on this topic has used a number of 2x2 Kronecker factors to reach the size of the weight matrix desired. This, however, leads to a dramatic increase in run-time.
Our technique restricts the number of factors to 2 and uses the prime factors of the weight matrix dimensions to find factor matrices as large as possible, thereby reducing the amount of computation required at inference. Results on an LSTM-based keyword spotting workload are shown below, where this technique achieved a 25x reduction in the model size:
Here, the Kronecker technique is compared to other state-of-the-art compression techniques, and an alternative version of the baseline made with fewer parameters. All of these points assume a 25x compression of the model. While the Kronecker technique is slower than the alternatives, it is still faster than the baseline and preserves the most accuracy.
One restriction of the Kronecker technique is that the amount of compression cannot be “user-driven” as it depends on the dimensions of the factor matrices. We propose an additional “hybrid” Kronecker technique in our work, which gives a model designer flexibility in the amount of compression they want for a target model accuracy.
The Kronecker and Hybrid Kronecker techniques can be used as drop-in replacements for most RNN layers, and can be used selectively based on the target accuracy, model size and execution time. Our experiments show compression ratios from 10x to 38x using these techniques with minimal accuracy loss, enabling more and richer applications to run on constrained platforms.
The Kronecker version of the keyword spotting application has a model size of only 16kB, compared to the original 244kB. We were also able to reduce a human activity recognition model from 1.5MB to just 75kB – a 28x reduction. An already optimized USPS digit-recognition model which was already small at 8kB, is shrunk to under 2kB. Making complex networks smaller, and making small networks smaller still enables new applications to run on Arm microcontrollers, and enables those that already do to run on smaller, more power-efficient ones.
Pruning and matrix decomposition are popular ways to reduce model size, but we sometimes find that certain revolutionary neural architecture design choices have a significant impact as well. This is certainly the case with the depth-wise separable convolution popularized in the MobileNet networks. The authors of this paper also found that using depth-wise separable convolutions was the best way to get the most accurate, fastest, and smallest keyword-spotting model when compared to several other techniques.
But can we go further?
Two recent techniques – Bonsai Trees and StrassenNets – showed impressive results in reducing model size and computation. We applied these techniques individually to the most efficient DS-CNN depth-wise separable network in the Ternary Hybrid Neural-tree Network paper.
What we initially found was somewhat discouraging. Using StrassenNets resulted in dramatic reduction in model size due to its use of ternary weights but led to a significant increase in the amount of computation required. Bonsai Trees had the opposite effect – a reduction in execution time but an increase in model size.
We observed that different parts of the DS-CNN network responded differently to these two techniques. This led us to the HybridNet network architecture, shown below, that combines both of these ideas.
We preserved much of the original neural network in the feature extraction parts of DS-CNN and optimized it with the StrassenNets technique. We then optimized the classification layers using the Bonsai Decision Trees.
This new network architecture led to a 30% reduction in the overall memory footprint of the network, and a 12% reduction in the amount of computation. It achieved all of this while having a minimal impact on the model accuracy of only 0.3%.
HybridNet illustrates how innovatively combining several known techniques leads to new levels of optimization. More details on this work can be found in our SysML 2019 paper, 'Ternary Hybrid Neural-tree Networks for Highly Constrained IoT Applications'. The Arm ML Research group are continuing to improve on these techniques, trying to find ways to mitigate the overheads even further.
The Cortex-M4F is frequently used in chips that have 32kB or less data RAM capacity. Reducing the memory footprint of keyword spotting, and other such similar workloads, will allow us to deploy machine learning on hundreds more SoCs and innumerable more IoT devices.
Our Kronecker and HybridNet work illustrate the two-pronged approach we are taking in our TinyML work at Arm, and the significant optimization improvements that have been achieved so far. So, what’s next? Our team is focusing on both uncovering new algorithms for aggressively optimizing ML models, while simultaneously trying to combine a variety of these algorithms to best address the diverse landscape of neural networks. We’re excited to drive these improvements forward and pave the way for continued innovation across the Arm ML ecosystem.
This blog post was authored by the Arm ML Research Lab
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There is a chain of reasoning you can follow using random projections that would suggest that having n weighted sums operating on a single common vector of nonlinear terms is very wasteful in the number of parameters used. This may be a reason why pruning is so effective with conventional neural networks.
Anyway the computational cost per layer is O(n^2) which is almost a guarantee that the hardware will run sizzling hot and pull a lot of power.
How nice it would be if there was an O(nlog(n)) per layer neural network. The hardware could run both cool and fast.
Thanks for the link to the Bonsai algorithm by the way.