Interconnects are metal wires that electrically connect transistors with each other and ultimately to the outside world through input and output pins, making an integrated circuit (IC) functional. They play a critical role in enabling high-performance logic and memory in today's most advanced chips. Over the years, the scaling of feature dimensions has improved transistor delay (due to shorter channel lengths) but worsened the wire resistance-capacitance (RC) delay. Traditionally, the interconnect pitch scaling causes wire resistance increase, and the resistance dominates the transistor itself. However, this is no longer the case for deeply scaled nodes with narrow critical dimensions of metals; the wire resistance is now in the same order as the transistor resistance. Copper (Cu), a widely used metal in modern interconnects, utilizes a barrier to prevent metal diffusion into the adjacent dielectrics and a liner to promote metal fill. Dielectrics are materials, like SiO2, sandwiched between the wires to provide electrical isolation from neighbors. Cu suffers from a rapid increase in resistivity at narrow critical dimensions due to increased electron scattering at the metal-dielectric surfaces and metal-grain-boundary interfaces. In addition, the thicknesses of the much higher resistance liner and barrier are scaling at a much slower rate than the wire dimensions themselves. This leads to proportionally lower Cu volume in the wires, causing an increase in the wire resistance. Therefore, interconnects quickly become the bottleneck for improving IC performance, so exploring lower signal routing delay is essential.
While traditional wires are fabricated in the back-end-of-line (BEOL) "above" the transistors, buried interconnects have been proposed as metal wires "buried" in the front-end-of-line (FEOL) oxide or silicon substrate "below" the transistors. While the buried interconnections provide an alternate layer for connectivity, the buried metals must withstand the front-end-of-line (FEOL) process thermal budget. Ruthenium (Ru) is one such metal that can survive these high temperatures, also offering lower resistivity in narrow wires and a higher metal volume ratio than Cu. These buried wires can be made tall with demonstrated aspect ratios of up to seven [1]. Due to their typically tall dimensions, buried wires have higher capacitance and lower resistance, ideal for power and ground routing. A previous study completed by Arm Research on a Cortex-A53 "LITTLE" core showed that such Buried Power Rails (BPR) could help reduce the worst-case IR voltage drop by 1.7X to 7X at a 3nm process node [2]. For a high-level view, look at this blog post. BPR is a critical scaling booster on the technology scaling roadmap and is an active area of interest for both design houses and foundries.
We explored the use of buried interconnects in SRAM designs to reduce the resistance of critical signal routing and presented our work at the 66th International Electron Devices Meeting (IEDM) [3]. We partnered with imec to generalize and adapt the BPR process for critical signal usage. We also collaborated with Synopsys for their tool expertise on buried signal parasitic RC extraction. Wordlines and bitlines in SRAM were identified as possible preliminary candidates for buried signaling due to their criticality to SRAM power and performance. Moreover, these signals are routed in long metal wires of lower back-end-of-line (BEOL) layers, making them highly resistive. For example, scaling from the 16nm process node to the 3nm process node has increased the resistance of those metals by 2-3.5X (figure 1).
Figure 1: Resistance scaling trends for SRAM wordline and bitline for 1-1-1 FinFET (high-density), and 1-2-2 FinFET (high-performance) bitcells.
In advanced FinFET SRAMs, the bitlines are routed along the direction of the fins, while wordlines are routed perpendicular to the fin. Due to this reason, it turns out that buried wordlines would require a significant process change from the BPR approach. Hence, we selected bitlines for our analysis to minimize any process cost addition to BPR. We reported a novel SRAM cell design with a buried interconnect used for routing the bitlines (figure 2).
Figure 2: Schematic, layout, and cross-sectional views of 1-1-1 SRAM cell with buried bitline, drawn using imec's N5 process node design rules.
The capacitance of the bitline wires directly impacts the SRAM read operation speed and dynamic power. It was critical to comprehensively analyze the coupling of buried bitline wires to the neighboring metal wires, devices, and the silicon substrate. Accordingly, high-accuracy 3D field solver-based parasitic extraction of the buried bitline SRAM cell was performed using Synopsys QuickCap® NX. It was found that buried bitline capacitance with the default BPR thickness (height) would lead to high bitline capacitance, severely degrading SRAM power and performance. Next, we performed a detailed design-technology co-optimization (DTCO) analysis to find the dimensions of buried metal for optimal bitline signal RC delay. Finally, we evaluated macro-level metrics to quantify the improvement from buried bitline on SRAM performance and power. We found that buried bitline SRAM can improve access time by up to 11%, write time by up to 31%, and dynamic power by 4%. This improvement is effectively equivalent to one complete technology-node scaling gain [4], demonstrating the effectiveness of buried interconnects for signal routing.
To the best of our knowledge, this was the first work exploring the use of buried metals for signal routing. Our findings suggest that buried interconnects, if carefully sized, can help mitigate the interconnect resistance issue and augment the technology scaling roadmap for sub-5nm process nodes. This work paves the way for other buried signals like wordlines and clocks in future IC designs.
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Paper Reference: "Buried Bitline for sub-5nm SRAM Design", R. Mathur, M. Bhargava, S. Salahuddin, P. Schuddinck, J. Ryckaert, S. Annamalai, A. Gupta, Y. K. Chong, S. Sinha, B. Cline, J. P. Kulkarni, IEEE International Electron Devices Meeting (IEDM), 2020.
[1] A. Gupta et al., "High-aspect-ratio ruthenium lines for buried power rail," in 2018 IEEE International Interconnect Technology Conference (IITC), pp. 4–6, 2018.
[2] D. Prasad et al., "Buried Power Rails and Back-side Power Grids: Arm® CPU Power Delivery Network Design Beyond 5nm," 2019 IEEE International Electron Devices Meeting (IEDM), 2019, pp. 19.1.1-19.1.4.
[3] R. Mathur et al., "Buried Bitline for sub-5nm SRAM Design," 2020 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2020, pp. 20.2.1-20.2.4.
[4] H. C. Lo et al., "A 12nm FinFET Technology Featuring 2nd Generation FinFET for Low Power and High-Performance Applications," 2018 IEEE Symposium on VLSI Technology, 2018, pp. 215-216.