Architectural tricks to maximize memory bandwidth

Unexplained Read/Write latency can be attributed to cache hit-ratio, burst length, commands-in-a-row, AXI Bus arbitration, and video pipeline. During this Webinar, we will present the system-level modeling of complex video pipelines and their interface to memory using a Network of Buses. With this model, we shall optimize the address allocation to IP blocks, burst lengths and memory controller settings to get close to 98% efficiency.