Consider Data interface is 64 bit.It is Write transfer.AXI master need to transfer 11 bytes and starting address is 0. Anyone suggest which one is a valid among below mentioned two scenarios.
Scenario 1:Burst -> Address:0, size:3, length:1, burst_type:11st transfer -> placing 1st 8 bytes with write-stobe 8'hFF 2nd transfer -> Placing remaining 3 bytes with write-strobe 8'h07
Scenario 2:Burst(1) -> Address:0, size:3, length:0, burst_type:1Transfer -> placing 8 bytes with write-stobe 8'hFF
Burst(2) -> Address:8, size:1, length:0, burst_type:1Transfer -> placing 2 bytes with write-stobe 8'h03
Burst(3) -> Address:10, size:0, length:0, burst_type:1Transfer -> placing 1 byte with write-stobe 8'h04
Both scenarios are valid, but your second one is much more complex than the first, so not what I would suggest you use. Scenario 1 is nice and simple and legal.
Was the scenario 2 description an attempt to avoid using WSTRB to indicate the active byte lanes where they are narrower than the AWSIZE indication ? All AXI slaves should support any legal use of WSTRB, so this burst complexity shouldn't be required.
Thanks for the answer. But my doubt is, what is the significance of having AWSIZE signal in the AXI interface. We can smoothly manage write transaction, only with WSTRB signal right?
You need AWSIZE so that the slave knows by how much to increment the address in each beat of a burst. AWADDR only gives you the start address for the burst.
WSTRB then indicates which bytes within the AWSIZE indicated transfer width that are to be updated in the slave.
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