I have a scenario where on the first transfer and only transfer byte of a read transfer.
HREADY is high. HTRANS = NONSEQ.
On the 2nd HCLK (data phase), HREADY goes low. What should be the expected value on HTRANS at this time?
I'm currently driving it to 00 (IDLE), but we are debating if it should retain the NONSEQ value instead of updating to IDLE.
Please see screenshot attached for reference.
AHB transfers occur over 2 separate "phases".The "address phase" when the HTRANS transfer type is signalled, and the "data phase" when the target device performs the requested transfer.
During the data phase of a transfer, the address phase control signals signal the NEXT transfer that will be requested, so a pipelined operation.
So if you only want to transfer one byte, so only have one transfer to request, HTRANS would be driven to IDLE for the next transfer address phase, while your current transfer data phase is being performed (including any wait states that data phase might require).
See for example figure 3-6 in the AHB-lite spec, showing the pipelining of a series of transfers, and how the data phase for each transfer follows the address phase of that transfer, with HTRANS signalled in the address phase ahead of HREADY and HRDATA/HWDATA in the data phase.
There isn't any diagram showing all the signals when you are just performing a single one-off transfer, but once you see the pipelining and the separate address and data phases, the only appropriate HTRANS value following a NONSEQ address phase when you only have one transfer to perform is IDLE as that is what you signal when you have no transfer to request.
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