AHB3_Lite protocol has a paragraph that "All transfers in a burst must be aligned to the address boundary equal to the size of the transfer. For example, you must align word transfers to word address boundaries(HADDR[1:0] = b00), and halfword transfers to halfword address boundaries (HADDR = 0). The address for IDLE transfers must also be aligned, otherwise during simulation it is likely that bus monitors could report spurious warnings."
So is this meaning that AHB3_Lite master interface can never send an address like 0x01 when transfer type is halfword and never send address like 0x03/0x02/0x01 when transfer type is word?
I'm designing a bridge from AHB3_Lite to AXI4, if my understanding is right, this means AXI4 interface don't need to deal with unaligned address because AHB3_Lite interface never send sucn address. Is it right?
Just for your information I have moved your thread to the SoC forum where it should live.
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