AXI4-Relationships between the channels

A statement in AXI4 specification says that " the write data can appear at an interface before the write address that relates to it. This can occur when the write address channel contains more register stages than the write data channel. It is also possible for the write data to appear in the same cycle as the address."

Please explain, why the need of register stages arises here?

Is that every AXI master component needs to have register stages? Why?

  • Register stages can be added to any AXI channel to help meet timing on long paths.

    So for this statement you refer to it is looking at when perhaps the AXI master issued its AW and first W channel transfers; they were issued in the same cycle, but because the address path was more complex it needed breaking up into two shorter paths to meet single cycle timing on each half of the path, resulting in the AW transfer being seen at the AXI slave one cycle later than the W data transfer.

    Register stages (sometimes called Register Slices) are not always needed in a design, but are used to help meet timing path requirements. They can be added at any point on a path between master and slave, on any channel or group of channels.

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