This is not really SoC design question, more processor type, but I didn't see such forum here. So , excuse me if not really on topic.
My question is, is benefit of pipeline directly reduced by the number of interrupts serviced? Because of flushing / refilling it each time , from jumping to serve an ISR, and then jumping/ returning back.
Is this like, a direct relationship? 10% increase in interrupts handled, 10% decrease in pipeline performance..? Or is this totally wrong.