The CHI protocol spec mentions 2 additional cache line states as compared to AXI viz., Unique Clean Empty and Unique Dirty Partial. What is the reason for introducing two additional cache line states and what are the scenarios/use-cases in which a cache line can assume these states? If some reference state diagram is available, it will be helpful.
Unique Clean Empty is helpful to describe scenarios where it is guaranteed that no other RN has this cache line (i.e. it can be Unique), but the RN does not have any valid data for that line (i.e. Empty).
For example, an RN issues a CleanUnique. The RN loses the line via a snoop before the CleanUnique completes. At the point the CleanUnique completes, the line has been invalidated in all other RNs, but the initiating RN does not have any data for that line as a CleanUnique completes without returning any information.
Unique Dirty Partial allows a cache line to have multiple dirty bits within a cache line, which would allows the RN to be more precise with how much data needs to be written back to main memory. For example, if only a part of the cache line was Dirty, the RN could use WriteBackPtl instead of writing back bytes that are already up to date in memory.
Cache transitions are given in Section 4.7 of the CHI Spec.