Atomic access LDR/STR vs LDREX/STREX

I'm working with the obsfucated RTL for Cortex-M3. I have a working design that muxes the 3 AHB-lite buses to 2 AXI3 buses. This design is analogous to the Xilinx designstart design with a code bus and a system bus. The processor correctly boot from the code bus and executes instructions (ITCM disabled). The problem is I see no difference on the AXI bus between normal LDR/STR and LDREX/STREX. I had expected AxLOCK to be set so a monitor can be implemented according to : http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dht0008a/CJAGCFAF.html

No matter what I try it appears the STREX instruction fails (returns 1). Even when BRESP is set to 2'b01 after the write. All of this would be fine if it worked properly with the DTCM enabled but those exclusive writes fail as well...

Any ideas on what else to check?

How does the AHB-lite bus handle exclusive access? Maybe something is missing in the translation?

Thanks!

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  • Finally got this working... The key is the TRM for the XHB-400 corelink bridge.

    http://infocenter.arm.com/help/topic/com.arm.doc.ddi0523a/DDI0523A_corelink_xhb400_axi4_to_ahb_lite_bridge_r0p0_trm.pdf

    My final solution takes EXREQ/EXRESP into the AHB-lite to AXI3 bridge. EXREQ gets converted to the AxLOCK signal. The global monitor sits on the AXI3 bus and manages transactions. If there weren't any invalidating transactions between the LDREX and STREX then BRESP=2'b01=EX_OKAY. BRESP propagates back to clear the EXRESP signal (active low) in the proper cycle. Not sure this is all correct but it works in my testing.

    It would be nice if CLREX could clear the global monitor but I can't figure out how to do that. I'm guessing I would need to plumb it all the way into the core. My understanding is this isn't needed for single-processor systems.

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  • Finally got this working... The key is the TRM for the XHB-400 corelink bridge.

    http://infocenter.arm.com/help/topic/com.arm.doc.ddi0523a/DDI0523A_corelink_xhb400_axi4_to_ahb_lite_bridge_r0p0_trm.pdf

    My final solution takes EXREQ/EXRESP into the AHB-lite to AXI3 bridge. EXREQ gets converted to the AxLOCK signal. The global monitor sits on the AXI3 bus and manages transactions. If there weren't any invalidating transactions between the LDREX and STREX then BRESP=2'b01=EX_OKAY. BRESP propagates back to clear the EXRESP signal (active low) in the proper cycle. Not sure this is all correct but it works in my testing.

    It would be nice if CLREX could clear the global monitor but I can't figure out how to do that. I'm guessing I would need to plumb it all the way into the core. My understanding is this isn't needed for single-processor systems.

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