About AXI protocol Specification

Under the section of "About the AXI protocol" specification states that AXI Protocol "meets the interface requirement of the wide range of component"

please elaborate in a wider sense?

Parents
  • The various statements made at the start of the AXI protocol are just very vague points to try to show that it could be suited to a wide variety of applications. I wouldn't try to read too much into them, I usually ignore any comments like these and only start asking questions once I get into the detail in the protocol.

    However to answer this specific question I guess the protocol designer is observing that there is no one interface type that the protocol is restricted to. The very loose timing requirements between the address, data and response channels, and the read and write channels, makes this protocol suitable for very closely timing related interfaces such as SRAM type interfaces where the address and write data transfers occcur at the same time, less tightly aligned interfaces such as DRAM where knowing the address well in advance of the data is better, and also complex multi-threaded processor type interfaces where all the out-of-order and different ID transaction support allows a lot of flexibility.

    But again everything I've just written in that last sentence is still vague references, and I would also ignore all of that and just jump into the details in the protocol specification. Don't get bogged down in detail too quickly :)

Reply
  • The various statements made at the start of the AXI protocol are just very vague points to try to show that it could be suited to a wide variety of applications. I wouldn't try to read too much into them, I usually ignore any comments like these and only start asking questions once I get into the detail in the protocol.

    However to answer this specific question I guess the protocol designer is observing that there is no one interface type that the protocol is restricted to. The very loose timing requirements between the address, data and response channels, and the read and write channels, makes this protocol suitable for very closely timing related interfaces such as SRAM type interfaces where the address and write data transfers occcur at the same time, less tightly aligned interfaces such as DRAM where knowing the address well in advance of the data is better, and also complex multi-threaded processor type interfaces where all the out-of-order and different ID transaction support allows a lot of flexibility.

    But again everything I've just written in that last sentence is still vague references, and I would also ignore all of that and just jump into the details in the protocol specification. Don't get bogged down in detail too quickly :)

Children
No data
More questions in this forum