I have an AXI master with data width 64, and an AHB slave of data width 32. What would happen when there is a 64bit FIXED burst READ (i.e., asize=3)to an address 0X100 of the slave?
Would the the data be read from 0x100 only, with data[63:32] always 0? Or would the data be read from 0x100 and 0x104?
The AXI FIXED transaction is accessing byte addresses 0x100-0x107 with each transfer, so the downsizing logic on this path would have to convert each FIXED transfer into a 32-bit 2-beat INCR transaction starting at 0x100 to cover the same address range.
So the correct solution would be the second of your two suggestions.
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