I am new to AXI protocol. Though I have read the document of AXI , but have some doubts on it. I have made run a write sequence (only from AXI to get the better understanding ) Please have a look at the following waveform.
In this diagram , I have made incr type burst request.
In between I am getting the protocol is generating awvalid in between , shouldn't it be asserted only once for each time a transaction is made ?
Please help me out here ? Am I missing something.
In theory there is nothing wrong with your waveform diagram.
The master has performed a 16 transfer INCR burst, and after the 16th write data transfer with WLAST correctly high you see the BRESP response come back.
However after this 16th write data transfer you then see further W channel transfers, and also then some AW channel transfers. From a protocol perspective there is nothing wrong with these as a master can issue multiple transactions. W channel transfers can happen ahead of AW transfers, and you can have multiple active AW transfers outstanding.
So is the issue just that you were not expecting these further transfers ?
What is the AXI master that is sending these transfers, is it a real processor that has moved on to performing other tranfers, or a test master that you tightly control which is issuing unexpected or incorrect transfers ?
Yuo need to look at the AXI master to see why these transfers have occured after your 16-beat INCR burst has completed.
One observation on your waveforms, why is AWLEN of width [9:0] and BRESP of width [3:0] ?
AWLEN should be [7:0] for AXI4 or [3:0] for AXI3, and BRESP is [1:0].
View all questions in SoC Design forum