The transfers in AHB protocols occur in two phases - address phase and data phase. Does this mean that the processor (Master) must have pipelined architecture?
It's what the protocol is designed to work with, so unfortunately yes.
In theory if you have a non-pipelined master architecture, with all the address and data information being signalled in one cycle (perhaps 2 cycles for reads ?), each access to the AHB will then need to take a minimum of 2 clock cycles to allow your AHB interface logic to generate the separate address and data phase operations, with that data phase length then being determined by the response from the slave.
Again in theory you could then use BUSY transfers on HTRANS while you are waiting for each data phase to complete to try to support bursts, but only if that will improve the performance of the slave.
But using AHB for this design isn't going to result in a high performance solution as the protocol is really designed to work with masters working with pipelined transfers, so the AHB interface to your non-pipelined architecture is going to have to create the pipelining for you.
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