AXI3 write data interleaving with same AWID

This is regarding the AXI3 write data interleaving. I understand how the write data interleaving works when AWID=WID when a slave is accessed by multi masters or a single master which can generate multiple outstanding transactions. But I have a query on below line item 

The Write data interleaving of AXI protocol specification says:  

"A master interface that is capable of generating write data with only one AWID value generates all write data in the same order in which it issues the addresses. However, a master interface can interleave write data with different WID values if the slave interface has a write data interleaving depth greater than one".

My understanding is:

Consider a single master which supports interleaving and can generate max of 4 interleaved transactions (A, B, C, D) to a slave. Here A, B, C, D are WID values and AWID is a constant value (where AWID not required to match any of WID value or simple tied to zeros). The address for all these transactions let us say Aa, Ba, Ca, Da. 

For example, If master issues addresses in the order Ba, Ca, Aa, Da, then the first data item of a write should be in the same order. In this case, the valid order can be B0, C0, C1, A0, A1, D0, B1, C2, A2, A3, D1 D2 or simply B0, C0, A0, D0, B1, C1, A1, D1. Here the address, WID and its order can help slave to identify where to write the data in its local address space.

Can please check whether my understanding is correct ?. Also can you please provide a use-case where a master can issue single AWID and multiple WIDs. 


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