This is regarding the AXI3 write data interleaving. I understand how the write data interleaving works when AWID=WID when a slave is accessed by multi masters or a single master which can generate multiple outstanding transactions. But I have a query on below line item
The Write data interleaving of AXI protocol specification says:
"A master interface that is capable of generating write data with only one AWID value generates all write data in the same order in which it issues the addresses. However, a master interface can interleave write data with different WID values if the slave interface has a write data interleaving depth greater than one".
My understanding is:
Consider a single master which supports interleaving and can generate max of 4 interleaved transactions (A, B, C, D) to a slave. Here A, B, C, D are WID values and AWID is a constant value (where AWID not required to match any of WID value or simple tied to zeros). The address for all these transactions let us say Aa, Ba, Ca, Da.
For example, If master issues addresses in the order Ba, Ca, Aa, Da, then the first data item of a write should be in the same order. In this case, the valid order can be B0, C0, C1, A0, A1, D0, B1, C2, A2, A3, D1 D2 or simply B0, C0, A0, D0, B1, C1, A1, D1. Here the address, WID and its order can help slave to identify where to write the data in its local address space.
Can please check whether my understanding is correct ?. Also can you please provide a use-case where a master can issue single AWID and multiple WIDs.
Unfortunately your whole question fails because the AWID value for a transaction must match the WID value for that transaction. It is the IDs that tell the master and slave which transaction the address, data and response transfers refer to.
So you cannot have a master issuing just one AWID value but multiple WID values.
Thanks for the comments.
Yes, AWID should match WID. But below statement gives interleaving w.r.to WID alone ? So do you think below statement is not valid now or no system is implemented with this ?
"A master interface that is capable of generating write data with only one AWID value generates all write data in the same order in which it issues the addresses. However, a master interface can interleave write data with different WID values if the slave interface has a write data interleaving depth greater than one" -> statement is invalid.
The AXI protocol operates by using IDs to tie together the separate channels used in an operation. Understanding this is one of the basic functions described at the start of the protocol, so by the time you reach more complex sections of the protocol such as this, it is expected that this function is understood and doesn't need repeating.
I agree that taking this statement in complete isolation does allow for an undertanding that you could have multiple W channel transfers with different WID values all related to single AWID values, but you cannot take one statement late in a protocol and expect it to be fully understood in complete isolation. Otherwise to make every statement self supporting would mean repeating basic concepts throughout the protocol document.
Systems CAN be implemented using write data interleaving IF they follow all other requirements of the protocol not detailed in this one statement, although you will notice that write data interleaving has been removed from the later AXI4 protocol as it was found that most (perhaps even all) designs did not use it due to the complexity it adds at source and destination. Instead designers preferred to buffer up write data at source and only send it in one transaction of consecutive transfers when all the data was available (removing the need to require interleaving to make use of wasted data bus bandwidth in between sporadic write data transfers).
Thanks for the description. I got your point.
Yes, in AXI4 write data interleaving is removed which reduces the complexity of managing multiple outstanding transactions at master and slave. (Instead buffering is simple to implement)