A couple of further details on the question.
Let's assume that I have a 64-bit data bus and a 32-bit address bus.
A master issues a WRAP burst with AWADDR[31:0] = 32'd8 and AWSIZE[2:0] = 3'b110. That is, the start address is 8 and the beat size is 64 bits (thus the burst is non-narrow).
I am trying to understand if there are any restrictions on the value of WSTRB[7:0]: can the master disable byte lanes in this burst?
Thanks in advance for your help.
The only relevant protocol restriction here is that the start address of a WRAP transaction must be aligned to the AWSIZE (width) of the transaction, so assuming your AWSIZE value was actually 3'b011 (see note below), the start address is correctly aligned.
WSTRB can signal any combination of valid byte lanes described by the AWADDR/AWSIZE/AWBURST control signals, so for 64-bit transfers on a 64-bit data bus WSTRB could have any value from 8'b00000000 to 8'b11111111 (including all the values in between these extremes signalling disabled byte lanes), and WSTRB can have a different value for each transfer in the transaction.
Note that AWSIZE=3'b110 indicates 64 BYTES per transfer, not BITS. The maximum AWSIZE value your master can signal is the physical data bus width, so 3'b011 in this example.
Thanks Colin, everything is clear now. My mistake on the encoding of AWSIZE, you are right.
View all questions in SoC Design forum