I have an issue for timing simulation with ARM standard library (especially full adder).There are 3 inputs (A,B,CI), 2 outputs (CO,S) for the full adder and it looks like missing specify statements for them.When CI == 0, A == 1, B == 1, the outputs should be CO = 1, S = 0. And when A,B fall, CO also falls to 0.If there is some delay between A and B falling time, CO has some output delay (SDF annotated or default delay).But if A and B fall at the exactly same time, CO has no output delay!. Is that normal ?In case of A,B rising at the same time, CO also has some delay.Every full adder in ARM standard cell libraries has the same specify description.In my case, it causes hold violations. But in STA, there is no problem.I've tested with VCS/IES. Does they need some special options ? Or need some other solutions ?