PSTRB signal indicates which byte lanes to update during a write transfer.
it shows that the bus contain valid data, when PSTRB[3:0]=1111.
why we need bus instead of single bit PSTRB signal?
In the APB spec in table 2.1 there is a description of each signal, and the description for PSTRB indicates...
"There is one write strobe for each eight bits of the write data bus.Therefore, PSTRB[n] corresponds to PWDATA[(8n + 7):(8n)]."
See also section 3.2 which describes the write strobes.
The APB write data bus PWDATA has a maximum (and typical) width of 32-bits, so 4 write strobe bits are required for that scenario.
If you have a system with a 16-bit or 8-bit PWDATA bus width, the width of PSTRB implemented would be narrower.
Hello sir, can you please guide me on how to calculate unaligned address for APB. For AXI we are using AWSIZE. So for APB which size should we use to calculate unaligned address?
The APB protocol doesn't support unaligned addresses. The APB tries to be as simple as possible, so complex access types are pointless complication.
So if you want to access an APB register, use a correctly aligned transfer (the alignment being defined by the width of the data bus implementation).
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