Hi All ,
Can anyone please tell the difference btw AXI3 and AXI4.
There are various changes.
AxLEN now 8 bits wide to support INCR bursts of up to 256 transfers
New AxQOS, AxREGION and xUSER signals.
AxLOCK now single bit as support for "locked" transfers dropped.
No WID signal now as interleaving of write data transfers no longer supported.
AxCACHE renamed to be the "modifiable" bit.
"Memory types" defined to describe various AxCACHE encodings, explaining how these transfers should be handled by the system.
Additional handshake rule describing that B channel response can only be returned after both the AW and final W channel transfers have completed.
New concepts of "single copy atomicity" and "multi-copy atomicity" to define when parts of transfers or transactions can be seen by other elements in the system.
I think those are all the changes (that I can remember).
Colin Campbell said:New AxQOS, AxREGION and xUSER signals.
can you please explain the functioning of these signals in detail?
The signals are described in some detail in sectoin A8.1, A8.2 and A8.3 in the AXI spec, so is there something described there that you require additional detail on ?
View all questions in SoC Design forum