The design is implemented on a System On Chip (SoC)
The processor is Cortex-M3 32-bit which is interfaced to an FPGA fabric where a processing of some variables will take place. The variables are sent from the processor to the FPGA fabric, and they are larger than 32-bit (example 128). Let's say that the design for example do this: var+a; where var is 128-bits which is send from the processor and a is a constant stored in the FPGA. Afterward, let's say that the result res=var+a; will be sent back to the processor.
The APB bus is 32-bit. In addition, there is a dedicated core to interface between the Microcontroller Subsystem (which contains the Cortex-M) and the FPGA fabric. Then I will need to write a HDL code that collects the data sent from the Cortex-M through the APB bus.
Can anybody clarify the concept behind the resizing:
- How the state machine for such process should be defined? - The reading of address and data from the APB bus interface. - The writing of data in the adequate address so that it will be sent to the APB bus interface.
Is there any code example or a tutorial in that context that I can lean from.