I want to know what is the GICv2 configuration to map an interrupt to FIQ and signal it to the ARM core and the configuration on the ARMv8 to raise that FIQ interrupt at EL1 exception level.
For the GICv2 configuration, this can be found in Table 2-3 of the GICv2 Architecture Specification. In short, you have to enable FIQEn is set, and that Group 0 interrupts are enabled and that the interrupt you're triggering is configured as Group 0. See below for more information.
Thanks Christopher for the answer. To configure the interrupt as Group 0, GICD_IGROUPRn registers is used right?
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