AHB-Lite IDLE and hready related queries

Hi,

Can someone clarify below queries I have wrt AHB-Lite,

  1. Is there any relation between HTRANS=IDLE and hready ? Like,
    1. Whenever IDLE comes hready is de-asserted (or)
    2. Whenever hready is de-asserted, master gives IDLE
  2. What is the maximum duration for IDLE transaction?
  3. Transaction mentioned below is valid or not
    1. Single transfer followed by IDLE for 100 clock cycles.
      1. NonSeq - Idle (For 100 clocks) - NonSeq
      2. In the above transfer, does data phase takes place in the idle cycle or in the succeeding NonSeq address phase?

Thanks a lot!

Parents
  • 1. HTRANS is a signal driven by the master in the address phase of a transfer, and HREADY is driven by the slave in the data phase of a transfer, so no simple relationship.

    However if you are looking at the data phase of that IDLE transfer, the protocol mandates that HREADY must be driven high (it's an IDLE transfer, the slave isn't being asked to do anything, so there is no reason for it to need to signal wait states).

    If you are looking at the address phase of an IDLE transfer, HREADY is currently being driven in response to the previous transfer address phase, so then you could see wait states being signalled (if that previous transfer address phase had signalled a NONSEQ or SEQ transfer), and because this is a pipelined bus protocol you see the current address phase IDLE transfer being extended.

    There is no link between HREADY being deasserted and the master having to signal IDLE transfers, or the master signalling IDLE transfers and the slave having to deassert HREADY. Doing this would wrongly stall the bus.

    2. The maximum duration of an IDLE transaction address phase is, as described above, dependent on the wait states being signalled for the previous transfer data phase. The maximum duration for an IDLE transfer data phase is 1 HCLK cycle, because there is a mandatory zero-wait OKAY response requirement here.

    3. You can have a single transfer (NONSEQ) followed by IDLE signalled for 100 clock cycles. The 100 clock cycles of IDLE could be because the single NONSEQ transfer resulted in 99 wait states (so extending the next IDLE transfer address phase for 100 cycles), or the NONSEQ transfer data phase could complete with no wait states, and this being followed by 100 IDLE transfers (each with a mandatory zero-wait response), or any mix of these two extremes.

    There is no limit to how many wait states can be signalled for a NONSEQ or SEQ transfer data phase, and there is no limit to the number of IDLE transfers a master could perform one after the other (that would just indicate the master has no need to use the bus). 

Reply
  • 1. HTRANS is a signal driven by the master in the address phase of a transfer, and HREADY is driven by the slave in the data phase of a transfer, so no simple relationship.

    However if you are looking at the data phase of that IDLE transfer, the protocol mandates that HREADY must be driven high (it's an IDLE transfer, the slave isn't being asked to do anything, so there is no reason for it to need to signal wait states).

    If you are looking at the address phase of an IDLE transfer, HREADY is currently being driven in response to the previous transfer address phase, so then you could see wait states being signalled (if that previous transfer address phase had signalled a NONSEQ or SEQ transfer), and because this is a pipelined bus protocol you see the current address phase IDLE transfer being extended.

    There is no link between HREADY being deasserted and the master having to signal IDLE transfers, or the master signalling IDLE transfers and the slave having to deassert HREADY. Doing this would wrongly stall the bus.

    2. The maximum duration of an IDLE transaction address phase is, as described above, dependent on the wait states being signalled for the previous transfer data phase. The maximum duration for an IDLE transfer data phase is 1 HCLK cycle, because there is a mandatory zero-wait OKAY response requirement here.

    3. You can have a single transfer (NONSEQ) followed by IDLE signalled for 100 clock cycles. The 100 clock cycles of IDLE could be because the single NONSEQ transfer resulted in 99 wait states (so extending the next IDLE transfer address phase for 100 cycles), or the NONSEQ transfer data phase could complete with no wait states, and this being followed by 100 IDLE transfers (each with a mandatory zero-wait response), or any mix of these two extremes.

    There is no limit to how many wait states can be signalled for a NONSEQ or SEQ transfer data phase, and there is no limit to the number of IDLE transfers a master could perform one after the other (that would just indicate the master has no need to use the bus). 

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