AXI4 - read data interleaving

Hi Folks,

We need a clarification on Read Data Interleaving on AXI4

Read Data Interleaving is supported in AXI4 and following is my understanding on Data Interleaving:

Multiple Read commands can be executed simultaneously and data interleaving is supported as long as all condition for ordering are followed.

I think data interleaving should not be done within a single burst. In other words, any single burst should contain data from single read command and no burst should contain data from multiple command.

I tried to confirm it but could not find a reference for it.

Can anyone confirm it or point me to a reference document for confirmation.

Thanks,

Amit

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  • Hi Amit,

    Hopefully the picture below can illustrate the permitted read data behavior.

    There are two AR transactions with different IDs. The RDATA in this example is both out of order and interleaved. It is just a mixture of the following two statements from the spec:

    ==========================================================

    Data from read transactions with different ARID values can arrive in any order.

    Read data of transactions with different ARID values can be interleaved.

    ==========================================================

    Regarding write data interleaving, the requirements are different from those for read data.

    AXI3: Write data interleaving (for different IDs) is supported. But the first item of write data must be issued in the same order as the write address.

    AXI4: Write data interleaving is not supported.

    Although write data interleaving is allowed in AXI3, masters developed by ARM (such as Cortex-R4) do not generate interleaved write data.

    Regards,

    Xingguang

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