how to calculate the value of strobe signal in axi?
The AXI write strobe signal is used to indicate which bytes of the write data bus are valid for each transfer of data. By using them you can perform sparse data transfers.
For example; when performing a write transaction on a 32 bit data bus, you will have a WSTRB signal that's 4 bits wide. Each bit of this WSTRB signal indicates whether or not the corresponding byte of the WDATA signal contains valid data that should be updated in memory for this transfer. The table below illustrates how each bit of the write strobe corresponds to a byte (8 bits) of the data signal, and will therefore indicates whether or not it is valid or not by being set to 1 or 0:
It's important to note that this write strobe signal can change for each item of data written in a write burst transaction.
I hope my explanation has clarified the purpose of this signal so you'll be able to successfully work out the value it should take, however if you need further clarification then please feel free to ask.
but how to calculate that strobe if my burst_size is = 4 and length = 4
If the burst_size is 4, do you mean that you are indicating 128-bit width transfers, and is this on a 128-bit data bus ?
If yes, that would mean you would have a 16-bit WSTRB bus (one bit for each byte of the data bus).
As David said in his reply 4 years ago, the master drives each WSTRB bit depending on whether that byte lane contains valid data for this transfer, so how you drive those 16 bits of WSTRB depends on what the master is trying to transfer.
And then if you have a burst of 4 transfers, the WSTRB value can be different for each of the 4 transfers in this burst.
Does that help answer your question, or can you explain with more detail what you are trying to do ?
Is it possible to re-calculate the WSTRB at the slave end for comparing against the WSTRB received from master. What are the parameters needed? Also what could be an algorithm (suitable for hardware implementation, i.e. one using muxes, shifters and not going for floor/ceil functions)? Note: Our slave calculates each of the beat addresses as a part of the application. Not sure whether the algorithm in A 3.4.1 of spec is suitable for hardware realization . Also any example illustration available to understand the equations in algorithm?
What if the size and len is 4 each and the data bus width is 256 bit ?? Kindly let me know the bits in strobe in this case. Basically I want to ask whether the strobe width depends on data width of the master or axsize?
The slave could theoretically check whether the WSTRBs send are legal (i.e. whether they're consistent with AxSIZE, AxADDR), but it couldn't always rely on recalculating it's own WSTRBs for legal combinations. If a master sends a sparse write (e.g. WSTRBs = 0b0101), then there's no way for the slave to reconstruct this using other attributes.
I don't think you would implement these functions exactly as they are described in the Specification, but you would implement equivalent functionality in hardware.
I'm not sure if there are any diagrams of this, but there's someone online AXI training material that is available at https://developer.arm.com/support/training
Yes, the WSTRB width directly relates to the data width. WSTRB Width = Data Bus Width (bits) / 8
The value of the WSTRBs also depend on the signalled AWSIZE. From A3.4.3 of the Spec - "A master must ensure that the write strobes are HIGH only for byte lanes that contain valid data." This means that if the AWSIZE indicates that access is narrower than the data bus width, then the strobes must not indicate more bytes are being transferred than AWSIZE indicates.
So with an example. If we have a 64 bit bus, and AWSIZE = 0x001 (2 bytes).
This means that the WSTRB width = 8. If AWADDR[2:0] = 0x0, then the only legal WSTRB values are: 0x00, 0x01, 0x02 and 0x03, as only the bottom two bytes can be valid.
Note AWADDR matters due to narrow transfers, as described in Section A3.4.3.
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