HREADY when no activity on bus


We are using ARM Matrix IP that is acting as a Master and using our VIP as a slave.

ARM Matrix is sending a initiating a WRITE Transfer on a slave when HREADY is low, but not keeping control signals stable till HREADY becomes high.

So the questions are

1) Is slave required to drive HREADY high when there is no active transfer? Isn't it possible that slave is busy with other activities and can't accept any new address?

2) Can address phase complete without being HREADY high? Mean as shown in attached snapshot, does Slave need to sample the address in a single cycle without HREADY being high?

3) In the protocol specs it is mentioned that "address_phase can't be stretched". Can you please elaborate that? Once Master have driven valid control signals, Slave can't drive HREADY low and must accept the address?

Appreciate your quick response.



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