Taking a major step forward for advanced-node semiconductor design, ARM and Cadence recently (April 4, 2013) announced the first implementation of an ARM® CortexTM-A57 processor on the TSMC 16nm FinFET manufacturing process. Here's a closer look at this groundbreaking test chip project, which used a complete Cadence Encounter RTL-to-signoff flow, Cadence Virtuoso custom design platform, ARM Artisan® standard-cell libraries, and TSMC's memory macros.
The overall goal of the project, according to Rahul Deokar, product marketing director at Cadence, was design acceleration. This aims to reduce the risk of a new process, facilitate the best possible power/performance for next-generation IP (ARM Cortex-A57 core in this case), and allow customers to get a head start on design flows using 16nm FinFET-ready tools.
In addition, Deokar noted that most test chips for new processes are small designs. "That's not sufficient to give a good feel for the big designs engineers will have to deal with later," he said. So in this case, using ARM's most sophisticated high-performance processor to date -- the Cortex-A57 processor, based on the ARMv8 Architecture -- on the test chip can provide additional learning that small test chip cannot. The Cortex-A57 core targets compute intensive applications such as high-end mobile computing and energy-efficient server and cloud computing. (For more information about the Cortex-A57 processor, visit the ARM web site).Co-optimizing Tools, IP and Process The test chip exercise provided a lot of opportunities for co-optimizing the process, EDA tools, and design IP. This requires a deeper and earlier level of collaboration compared to earlier process nodes. "There was a lot of iteration and learning going on between the process, the design, and the EDA flow," Deokar remarked. "The earlier the collaboration, the more each (participant) can influence the other in making the most optimal choices along the way."
The benefits of FinFET technology are clear. Basically, a FinFET is a new type of multi-gate 3D transistor that offers significant performance improvements and power reductions compared to existing planar transistors. A FinFET has lower threshold voltage, which results in faster switching and better performance. Better Ion control results in better leakage current and lower power. A generic FinFET depiction is shown at the right.
But FinFETs also pose some challenges for EDA tools. On the custom side, parasitic extraction must account for new R and C effects due to the 3D nature of the fins. Both Cgs (gate to source capacitance) and Cgd (gate to drain capacitance) become much larger, contributing to the Miller effect and impacting performance. Finally, transistor width cannot be changed arbitrarily, as it can for planar transistors -- designers can only add or subtract fins in discrete increments.
Deokar said that the Cadence Virtuoso platform and Cadence library characterization tools have been enhanced to address these challenges. These tools were used to develop libraries for the test chip exercise.
Digital Design Flow
For digital implementation of the ARM Cortex-A57 processor-based test chip, engineers used Cadence RTL Compiler Physical synthesis; Encounter Digital Implementation (EDI) System for place and route; and back-end signoff tools including QRC Extraction, Encounter Timing System (ETS), and Encounter Power System (EPS). The overall Cadence 16nm FinFET digital design flow is depicted below ("DPT" is double patterning).
A comprehensive 16nm support methodology was employed for the test chip effort. The methodology incorporated the new GigaOpt optimization technology to realize the power and performance benefits offered by FinFET technology.
Any 16nm FinFET digital flow requires double patterning, and support for this lithography technique has been available in Cadence digital tools since 20nm. Placement and routing are double-patterning aware, and can avoid the colorization (odd-cycle, same-mask) problems that may arise when two cells/layers are placed next to each other. Further, Deokar noted, Cadence extraction supports both double patterning and FinFETs.
In addition to support for electrical characteristics, the overall design methodology is important. A 16nm FinFET chip could contain hundreds of millions of gates in addition to a Cortex-A57 processor. As such, Deokar said, floor planning within a hierarchical flow is "absolutely critical," and that is why engineers used the Cadence First Encounter floor planning tool for the test chip effort.
The test chip project also used clock concurrent optimization (CCOpt), a new technology in Encounter that combines clock tree synthesis and physical optimization into a single step. Deokar noted that Cortex-A57 core clocking is sophisticated, with 3 or 4 levels of clock gating. CCOpt can perform a timing-driven optimization of clock trees and can skew clocks automatically. It therefore simplifies the clock tree development flow and promises better power and performance.
So what was learned from the test chip experience? "It takes a village," Deokar said. "No single company has everything that is needed for design acceleration at advanced nodes. It was necessary for Cadence, ARM and TSMC to work together and work earlier in the design cycle to bring this [test chip] to fruition. That's the biggest learning here. It's a significant milestone for the whole industry, and I think this tight collaboration model needs to continue going forward. This is the only way the risk of new process node adoption can be mitigated for all our mutual customers."
Partner Blogger:Richard Goering, Cadence, he started writing about EDA in 1985, when he was working for Computer Design magazine. He was the EE Times EDA editor for 17 years. He is currently senior manager of technical communications at Cadence, where he authors the Industry Insights blog.