Functional safety is becoming more critical across a range of markets and this has never been truer than in automotive systems as applications increasingly take more control of the vehicle’s primary functions.
For over two decades Arm has been developing products used in automotive and functional safety applications. Initially used in braking and airbag systems, Arm IP has been more recently adopted in Advanced Driver-Assistance Systems (ADAS) and autonomous driving applications to innovate and accelerate development. In parallel, the breadth and depth of Arm’s products supporting functional safety has also increased, with the level of technical safety requirements feeding directly into processor development.
Arm will be introducing a Software Test Library (STL) on the Cortex-A53 processor. This is the first applications processor to have self-test software provided by Arm. The availability of Arm’s first Software Test Library for an applications processor, which has been widely implemented in a range of automotive systems, will assist in supporting the increasing demand for functional safety enabled solutions for this challenging market.
In 2018, Arm introduced its Safety Ready portfolio which brings together all of Arm’s functional safety activities into one industry-leading program. It assists partners to achieve regulatory compliance with the provision of consistent comprehensive safety documentation developed within a rigorous process to enable shorter time to market for solutions with safety requirements. The Cortex-A53 STL will join the Safety Ready portfolio when it is released late this year.
Arm STLs are comprised of a suite of tests which can be executed on the processor to check the correct operation of its internal logic. The tests are used to detect stuck-at faults in the processor independently of the main application software execution flow.
The diagnostic coverage of the STL can vary and this is influenced by a number of characteristics. Precise coverage depends on elements such as the processor complexity, its selected configuration, the netlist and the regions of the processor with tests selected to be executed. The STLs provide an additional diagnostic mechanism which can be used to assist in achieving the overall system safety metric requirements. Each STL is developed for a specific processor and this enables the targeting of explicit nodes in the design. Arm has already enabled Cortex-M0+, Cortex-M3, Cortex-M4 and Cortex-R52 processors with new diagnostic capabilities through the creation of STLs.
Together with the Software Test Library code, a safety documentation package is also provided. This details information on the development activities of the STL and assists in its integration within the target system.
An STL can be run when required to detect permanent random single point faults in the core but can also be used to detect latent faults. Typically, they are used in systems with ASIL B requirements, but their latent fault detection capabilities also make them valuable in systems with ASIL D requirements. STLs can run on an existing design which has not been developed with a redundant version of the hardware, or where the cost or power of the added logic is undesirable. STLs may be used to provide diagnostic coverage which contributes to achieving ASIL fault metrics and can be integrated together with other system level fault detection mechanisms to assist in realizing safety goals.
New products coming to the market need to address the demands of functional safety and will often integrate fault detection and management features. The development of new silicon takes time, so adding diagnostic measures through software to existing products can help to accelerate deployment of solutions with higher levels of functional safety. STLs can be used on existing devices already available in silicon and in use in the market to help boost their diagnostic capability. They can also be used for new products, where software testing adds valuable flexibility. Arm is therefore committed to developing an extensive portfolio of STLs, some of which are already available today.
STLs offer a flexible approach to diagnostic testing which other approaches may not be able to achieve. As an example, Logic BIST needs to take the processor offline to perform testing. This demands enough time in the application to run the test or alternative resources to be available during testing which can be dynamically allocated to the task, replacing the hardware now under test. Alternatively, duplication of logic such as Dual Core Lock-Step can be used to provide a high level of diagnostic coverage, but this comes at the cost of power and area. An STL can be scheduled to run when needed, including during the application execution time without taking the processor off-line or needing to reset the core making them flexible to execute.
An STL can be executed in a single section or divided into short bursts of tests. This allows testing to be performed rapidly or alternatively when there are any available time slots within the normal execution of the application. The STL can be called with the preservation of the context being managed by the STL itself helping to simplify how to integrate the testing. An STL can also be run rapidly at boot time before control is handed over to the application. STLs are called by a handler, operating system or hypervisor to initiate their execution and can be scheduled to run within the Fault Diagnostic Time to detect errors in operation, allowing the application to meet its Fault Tolerant Time Interval (FTTI).
STLs can be used by chip integrators as part of their safety solution for a device and may be made available to users of these devices. Alternatively, users may opt to license the STL technology directly from Arm and to integrate this within their existing solution. Software can be simply called in the application or operating system to schedule execution flexibly when required.
The development of new silicon takes time, so adding diagnostic measures through software to existing products can help to accelerate deployment of solutions with higher levels of functional safety. The availability of Arm’s first Software Test Library for an applications processor will assist in supporting the increasing demand for functional safety enabled solutions and is an extension of a comprehensive product portfolio of processors. More information on Arm’s Software Test Libraries can be found on Arm.com.
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