The appetite for further autonomy in our vehicles is spurring advances in the underlying technology. As the number of sensors in and around the vehicle increases, so must the capability of CPUs for large-scale data processing. Traditional system designs with separate Electronic Control Units (ECUs) for the gateway, infotainment and Advanced Driver-Assistance Systems (ADAS), are making way for innovative approaches in fully integrated systems. These systems will consist of multiple applications running at different levels of Automotive Safety Integrity Level (ASIL). In order to realize fully autonomous vehicles in mass production, scalable, high performance computing with inherent safety is required.
The Cortex-A line of products has seen some very exciting innovation in microarchitecture design over the last decade. Some of my personal highlights include the introduction of coherent heterogeneous processing with big.LITTLE, native 64-bit support and a brand-new memory system with DynamIQ technology. Today sees another step change in the Cortex-A microarchitecture with the introduction of the automotive enhanced Arm Cortex-A76AE, the first high performance Cortex-A CPU with Split-Lock capability. Split for performance, lock for safety.
As the name suggests, the Cortex-A76AE is based on the recently announced, Cortex-A76 design. It is a superscalar, out-of-order processor that delivers similar levels of performance as the Cortex-A76 across integer, floating point, memory and machine learning, and achieves similar levels of energy efficiency. Where the Cortex-A76AE is different, is through microarchitectural upgrades for functional safety and added application flexibility.
The Cortex-A76AE is purpose-built for functional safety applications such as ADAS and autonomous vehicles. Let’s have a look at the main three benefits of the Cortex-A76AE.
Where the Cortex-A76AE really stands out, is in its ability to deliver the aforementioned performance, at high safety integrity. It achieves this through a significant redesign of the Cortex-A76, becoming the first high performance Cortex-A CPU to include the Dual Core Lock-Step (DCLS) and Split-Lock features. Configuring two CPU cores in ‘Lock-Step’ is a traditional way of achieving high levels of diagnostic coverage – the ability to detect the occurrence of an error condition.
The flexibility offered through Split-Lock also has a safety benefit. It can be extended to support potential fail-operational modes – the ability to continue to operate in a degraded mode rather than completely shutting the system down. For example, when running in lock mode, if one core starts to exhibit a failure condition, the system could be quiesced and the faulty core be taken off-line (split) allowing continuation in a degraded mode of operation. This ‘split available" capability is critical for any autonomous system. To find out more about how Split-Lock enables safer systems, check out our blog.
The following are the main microarchitectural highlights of Cortex-A76AE for safety:
Apart from the hardware features above, the Cortex-A76AE has been developed on an advanced process for the avoidance of systematic faults. This enables it to meet the ASIL D systematic requirements as standard.
Cortex-A76AE has been designed to act as the decision engine in next generation ADAS and Autonomous Vehicle systems. It delivers a 30% uplift in performance over its predecessor, the Cortex-A75, and a whopping 60% increase in performance over Cortex-A72. This massive boost in performance meets the emerging CPU requirements for autonomous driving of more than 250K DMIPS at less than 15 Watts for the compute cluster. This fits well within an SoC power budget of 30 Watts.
The microarchitecture of Cortex-A76AE is largely based on Cortex-A76, with the following highlights that deliver on performance:
As mentioned in the introduction, next generation ADAS and autonomous driving systems will consist of multiple applications running at different levels of safety criticality (i.e. different levels of ASIL). This presents a challenge to silicon providers when scoping the compute complex. How do you size-up the performance requirements five to six years ahead of knowing the exact mix of safety critical applications in a vehicle?
Cortex-A76AE solves the challenge of mixed criticality applications through its ability to operate in two modes, performance mode and safety mode. In performance mode, all cores within a cluster operate as Symmetrical Multiprocessors (SMP). In other words, a user is able to utilize all the compute resources within a cluster, coherently. In safety mode, pairs of Cortex-A76AE cores in a cluster are configured to run in Lock-Step.
A functionally-safe coherent interconnect such as the Arm CoreLink CMN-600AE, can support multiple clusters of Cortex-A76AE. In such a system, any mix of clusters can be run in performance mode and safety mode, to achieve a fine-grained balance to match the mix of safety critical applications. The mode of operation can be changed at any time through reset. This means that a Tier1 or car manufacturer is able to tune the platform to fit any mix of safety critical applications, post production.
This flexibility drastically improves the usability of platforms based on Cortex-A76AE, across multiple generations and market segments. To further aid configurability, the Cortex-A76AE is based on Arm DynamIQ technology, meaning that it is also extremely scalable in terms of performance, power and area.
It is an exciting time to be involved in the automotive market. The launch of the Cortex-A76AE and the Safety Ready program will enable countless innovations as we journey towards a fully autonomous future. Like to find out more? Then visit our Automotive Solutions page and keep a look out for our soon-to-be-announced webinars, where we will discuss this in more detail. Watch this space!
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