What is the priority between synchronous data abort and FIQ in Cortex-R5F?


With Cortex-R5F, we have a case where a read to the L2 memory generates both a synchronous data abort and an FIQ with near-zero delay. We are reading from RAM while the RAM is in test mode and corrupts the parity of the read command. The effect is that we are only seeing the FIQ. This is also true if with the debugger we put a HW breakpoint on both the data abort and the FIQ handlers: only the FIQ handler breakpoint is reached.

I would like to understand why that is what we are seeing. I am a bit surprised that the FIQ is as fast as the abort; indeed, the FIQ goes through multiple components, including an interrupt controller.

What we would like to know is:if the processor is ready to take simultaneously a synchronous data abort and an unmasked FIQ, to which does it give priority?

ARMv7-A/R Architecture Reference Manual §B1.8.2 "Exception priority order" -> "Architectural requirements for taking asynchronous exceptions" says:

"Within these limits, the prioritization of asynchronous exceptions relative to other exceptions, both synchronous and asynchronous, is IMPLEMENTATION DEFINED."

Meaning that the information is to be found in the Cortex-R5 Technical Reference Manual. However, I can't find it...

Thanks for your help.


More questions in this forum