Hello,
From the armv7 architecture, it mentions that all memory accesses to strongly-ordered memory occur in program order.
When switching from accessing the normal memory to strongly ordered memory, is memory barrier (__dmb() or __dsb()) necessary to ensure the data transfer to complete? Or in what situations, it may be required?
Thanks in advance.
Yes, a barrier is required. There's no guarantee of ordering between Normal and SO (or Device). Where ordering is important you'll need a barrier.
Can I ask what does order refer to in this case? Is it the instruction execute order or something else? For example, will processor optimize for the sequences of instructions for loading to normal memory and loading to strongly ordered memory?
From the Cortex R5 technical reference spec, it mentions that when accessing strongly ordered memory, the store buffer will be completely drained if I do not misunderstand. I am quite confused that it this is the case and instruction does not swap for accessing normal and strongly ordered memory, is memory barrier needed?
There is instruction ordering and memory ordering. Which are different, but related.
Re-ordering of instructions is something some processor pipelines do for performance. It should be invisible to software, and so usually don't need to worry about it too much. More an optimization question than functional correctness.
Memory re-ordering. Arm has a weakly-order memory model, which means that accesses might not be observed in the order they were issued by software. Example:
Initial value in memory: 0x0000PE X: STRB 0xA, [0x8000] <-- Store the value 0x0A to the byte at address 0x8000 STRB 0xB, [0x8001] <-- Store the value 0x0B to the byte at address 0x8001
PE Y: LDRH r0, [0x8000] <-- Load the 16 bits at address 0x8000
(Note: This isn't real code)
What value could be returned in r0 on PE Y? You might expect one of the following:
But with a weakly ordered memory model, PE A might have re-ordered it's two stores. Meaning this result is also possible:
This last result is perhaps unexpected if you just read the instruction sequences. If you need the access order to be preserved, then you can use a barrier:
PE X: STRB 0xA, [0x8000] <-- Store the value 0x0A to the byte at address 0x8000 DMB STRB 0xB, [0x8001] <-- Store the value 0x0B to the byte at address 0x8001
The DMB in this example ensures that the two stores cannot be re-ordered relative to each other. One way to think of this is that if you can see the second store, you must also be able to see the first. That is, it's not longer legal for PE Y to see B but not A.
All of the above assumes that the addresses in questions are marked as Normal. The rules for re-ordering for Device and Strongly Ordered regions are much stricter.
However, the thing that is easy to forget is that the stricter rules for (say) Strongly Ordered only applies relatives to other accesses also to Strongly Ordered regions. If the other access to is Normal (as in your question), you don't get the stricter rules