This may sound stupid but I'd like to confirm my understanding of the processor behavior, in the event of a Data Abort. Section 3.8 of the Cortex R5 Techincal Reference Manual explains the Exception handling by the processor and my current understanding is that after the abort handler (let's say software routine written in 'C' ) finishes, the processor will restart from the same instruction that caused the Data abort. So for example, let's say the following instruction generated Data Abort:
0x00007cfc: f8902040 ..@ LDRB r5,[r0,#0x40]
then after the software Abort handler is done completing it's work, the program execution will continue from the same address that generated Data abort (In this case, 0x00007cfc.). Please confirm if this understanding is indeed correct ?
Second question is that, what would be the value of R5 register (in this particular example) when the Data abort happened ? I think R5 should have undefined value, rather than actual value from the memory as pointed by R0 and the offset in this example. Please confirm.
Value of R5 is the one before the instruction.