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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3605 Questions
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  • Not Answered

    Forum FAQs 0

    • ARM Community
    8629 views
    0 replies
    Started over 5 years ago
    by Annie
  • Suggested Answer

    AXI4 BVALID Specification 0

    44 views
    1 reply
    Latest 5 hours ago
    by Ben Hicks Arm Employee Badge
  • Answered

    CHI: How to detect last flit of a multi-flit response 0

    • Cache coherency
    • AMBA 5 CHI
    29 views
    1 reply
    Latest 6 hours ago
    by Ben Hicks Arm Employee Badge
  • Answered

    Could you please explain the principle of associative replacement for ARMv7 L1 and L2 Cache sets 0

    396 views
    2 replies
    Latest 6 hours ago
    by weibin kong
  • Suggested Answer

    Which bit of WSTB should be set to 1? 0

    153 views
    1 reply
    Latest 9 days ago
    by Ben Hicks Arm Employee Badge
  • Not Answered

    Does gcc-arm-none-eabi-6-2017-q2-update-win32 support Cortex-A53 ? 0

    107 views
    0 replies
    Started 14 days ago
    by zb l
  • Suggested Answer

    AXI4 Channel Handshake 0

    • AXI4
    195 views
    1 reply
    Latest 20 days ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    Additional info on a particular MPU configuration 0

    • R5
    • Memory Protection Unit (MPU)
    289 views
    1 reply
    Latest 1 month ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    FPU op performance degradation in a very specific case 0

    • High Performance Computing (HPC)
    • performance
    299 views
    0 replies
    Started 1 month ago
    by Dmitrii Klementev
  • Not Answered

    a TCM ECC error can cause WFI to fail in the ARM R52+ architecture (Armv8‑R, Arch32) 0

    254 views
    0 replies
    Started 1 month ago
    by 1 1
  • Not Answered

    AFREADY reset value of ATB master I/F in CSTFunnel is 1'b0 0

    323 views
    0 replies
    Started 1 month ago
    by Nakhyeon Kim
  • Not Answered

    PMU IRQ-exception counts on Cortex-A76 overcount by EL2 timer amount — enabling EL2 counting makes it increase again (RK3588) 0

    • Cortex-A76
    • 12 (Debug Monitor)
    • Cortex-A55
    235 views
    0 replies
    Started 1 month ago
    by kw z
  • Not Answered

    "Test Target" instructions - only consider SAU / IDAU, or also PPC & MPC 0

    851 views
    1 reply
    Latest 1 month ago
    by ArmMadeMeCreateAName
  • Answered

    the AMBA AHB bus master interface to start a burst with only 1 data transfer without the HSEL signal 0

    • AHB
    275 views
    1 reply
    Latest 1 month ago
    by Colin Campbell Arm Employee Badge
  • Suggested Answer

    APB 0

    • APB
    239 views
    1 reply
    Latest 1 month ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Is it normal that DC CVAC does also carry out a cache line invalidate on Cortex-A53? 0

    • Cache coherency
    365 views
    2 replies
    Latest 1 month ago
    by Mario Trams
  • Answered

    Cortex-R52+ mode switch 0

    • Cortex-R52+
    459 views
    3 replies
    Latest 2 months ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

    More details on CSV2 0

    • Security
    • Branch Prediction
    713 views
    1 reply
    Latest 2 months ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    Unable to write to memory region marked as both writable and executable on cortex-R82 0

    • Cortex-R82
    • Memory Architecture
    559 views
    5 replies
    Latest 2 months ago
    by HamzaF
  • Not Answered

    M0 GPIO level-sensitive interrupt, how many minimal CPU cycles? 0

    • Cortex-M0
    • Interrupt Handling
    191 views
    0 replies
    Started 2 months ago
    by Liudr
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