hi ,
I want to know the cycle information ,latencies of each instruction(secially vector instructions in A32 and A64) in coretex A53 architecture. It seems there is no document available which specifies the cycle timings. Can any one please provide the information.Fast response will be appreciated.
Thanks,
Sujatha.
Hi ,
Can any one provide the information about cortex A -53 cycle information for instruction set.Fast response will be helpful for us.
Sujatha
Hi Sujatha,
Thank you for your question.
I'm afraid we do not publish this kind of detail for most of our processor cores, especially for the newer ones. May I ask what you are trying to achieve? Perhaps I can help in some other way?
Regards
Chris
Hi Chris,
Thank you for the reply.
I want to estimate how many cycles and latency's that a small portion of C code will take using AARCH64 and ARCH32 instruction set.I mean how many cycles generally it needs to execute the small portion of code?
Thanks for the extra information. In these situations, our suggestion is to use the performance counters in the processor to count cycles over short sequences. These are quite easy to use and well documented.
However, you should be aware that the cycle count information is not just dependent on the processor. Often the memory effects are much, much larger. If your sequence contains memory accesses, then the latency of these. and the resulting pipeline effects, are usually much greater than the cycles taken by the processor's execution units. They are also unpredictable, due to the non-determinate nature of cache behaviour.
The performance counters will show you the total effect of processor and memory, as well as allowing you to separate out stalls and latencies. A simple analysis of execution cycles taken from a manual will not show you any of this and is often not much use at all.
Hope this helps.
I hope you are trying to compute theoretical values for your piece of code. But most of the cases it won't help you.
If I am not wrong there are few other features like dual issue, branch predictor which plays vital role. If you want to profile your code then use performance counters. If you want to estimate for the product then you may need refer to drystone or coremark values and also your SoC implementation.
Hi all,
I am newbie for Cortex-a53. I am looking for something similar as Sujata mentioned. I want to count the cycles for execution of some functions. Is there anyway I can read cycles. I used to do this in cortex-15 as :
static void readticks(unsigned int *result)
{
struct timeval t;
unsigned int cc;
if (!enabled) {
asm volatile("mcr p15, 0, %0, c9, c12, 0" :: "r"(17));
asm volatile("mcr p15, 0, %0, c9, c12, 1" :: "r"(0x8000000f));
asm volatile("mcr p15, 0, %0, c9, c12, 3" :: "r"(0x8000000f));
enabled = 1;
}
asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r"(cc));
gettimeofday(&t,(struct timezone *) 0);
result[0] = cc;
result[1] = t.tv_usec;
result[2] = t.tv_sec;
Please suggest the modification I can do? or Can I use another method to read clock cycles count?
Rajeev
Hi,
Do you have any news about the availability of this guide for ARMv7-A ( Cortex A53) , with the number of cycles for each instruction?
I have to compare this theoretical number with the one I found reading the "Cycle Counter Register", so I can validate the value I am reading. Fast response will be appreciated.
Thank you in advance,
Larissa
Just read Chris' answer, the "theory" might not match the real life, as the cycle counts in a core manual do not reflect bus interactions.If you do not trust the performance counters, use another "time base", for example a timer in the SoC.