• State Accepted Answer
  • +1 person also asked this people also asked this
  • Locked Locked
  • Replies 1 reply
  • Subscribers 348 subscribers
  • Views 15848 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

ARMv8-A: Is an ISB instruction required after writing to the CPSR register in AARCH32 state?

Phenix Chen

For example, write cpsr as following code snippets:

mov r1, sp

movw lr, #0x393

movt lr, #0

msr cpsr_cxsf, lr

do_irq:

...

Is an ISB instruction required after "msr cpsr_cxsf, lr"?

Thank you in advance!

  • +1

    From the manual! (G1.10.1   Accessing PSTATE fields)
    "Writes to the CPSR have side-effects on various aspects of PE operation. All of these side-effects, except
    side-effects on memory accesses associated with fetching instructions, are synchronous to the CPSR write. This
    means that they are guaranteed:
    • Not to be visible to earlier instructions in the execution stream.
    • To be visible to later instructions in the execution stream."